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參數資料
| 型號： | FIN1218MTDX |
| 廠商： | Fairchild Semiconductor |
| 文件頁數： | 4/20頁 |
| 文件大小： | 0K |
| 描述： | IC SERIALIZER/DESERIAL 48-TSSOP |
| 標準包裝： | 1 |
| 功能： | 串行器/解串器 |
| 數據速率： | 1.785Gbps |
| 輸入類型： | LVDS |
| 輸出類型： | LVTTL |
| 輸入數： | 3 |
| 輸出數： | 21 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TFSOP（0.240"，6.10mm 寬） |
| 供應商設備封裝： | 48-TSSOP |
| 包裝： | 標準包裝 |
| 其它名稱： | FIN1218MTDXDKR |
2003 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FIN1215 / FIN1216 / FIN1217 Rev. 1.0.3
12
FIN
1215
/
FIN
1216
/
FIN
1217
—
LVD
S
21-
B
it
Serializers
/
D
e
-S
erializers
Receiver AC Electrical Characteristics (Continued)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
tRSPB0
Receiver Input Strobe Position of Bit 0
Figure 21
f=65MHz
0.7
1.4
ns
tRSPB1
Receiver Input Strobe Position of Bit 1
2.9
3.6
ns
tRSPB2
Receiver Input Strobe Position of Bit 2
5.1
5.8
ns
tRSPB3
Receiver Input Strobe Position of Bit 3
7.3
8.0
ns
tRSPB4
Receiver Input Strobe Position of Bit 4
9.5
10.2
ns
tRSPB5
Receiver Input Strobe Position of Bit 5
11.7
12.4
ns
tRSPB6
Receiver Input Strobe Position of Bit 6
13.9
14.6
ns
tRSPB0
Receiver Input Strobe Position of Bit 0
Figure 21
f=85MHz
FIN1218 only
0.49
1.19
ns
tRSPB1
Receiver Input Strobe Position of Bit 1
2.17
2.87
ns
tRSPB2
Receiver Input Strobe Position of Bit 2
3.85
4.55
ns
tRSPB3
Receiver Input Strobe Position of Bit 3
5.53
6.23
ns
tRSPB4
Receiver Input Strobe Position of Bit 4
7.21
7.91
ns
tRSPB5
Receiver Input Strobe Position of Bit 5
8.89
9.59
ns
tRSPB6
Receiver Input Strobe Position of Bit 6
10.57
11.27
ns
tRSKM
RxIn Skew Margin
(Error! Reference source not
found.)
f=40MHz, Figure 22
490
ps
f=65MHz, Figure 22
400
f=85MHz
FIN1218 only
Figure 22
252
tRPLLS
Receiver Phase Lock Loop Set Time
Figure 16
10.0
ms
Notes:
16. Total channel latency from serializer to deserializer is (T + tTCCD) + (2T + tRCCD).
17. Receiver skew margin is defined as the valid sampling window after considering potential setup/hold time and
minimum/maximum bit position.
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