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參數(shù)資料
| 型號： | FIN210ACMLX |
| 廠商： | Fairchild Semiconductor |
| 文件頁數(shù)： | 6/17頁 |
| 文件大小： | 0K |
| 描述： | IC SER/DES 10BIT 32-MLP |
| 標準包裝： | 3,000 |
| 功能： | 串行器/解串器 |
| 輸入類型： | LVCMOS |
| 輸出類型： | 串行 |
| 輸入數(shù)： | 10 |
| 輸出數(shù)： | 1 |
| 電源電壓： | 1.65 V ~ 3.6 V |
| 工作溫度： | -30°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-WFQFN 裸露焊盤 |
| 供應商設備封裝： | 32-MLP（5x5） |
| 包裝： | 帶卷 (TR) |
SC16IS741_1
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 29 April 2010
14 of 52
NXP Semiconductors
SC16IS741
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
DLL and DLH must be written to in order to program the baud rate. DLL and DLH are the
least significant and most significant byte of the baud rate divisor. If DLL and DLH are both
zero, the UART is effectively disabled, as no baud clock will be generated.
Remark: The programmable baud rate generator is provided to select both the transmit
and receive clock rates.
1.8432 MHz and 3.072 MHz, respectively.
Figure 11 shows the crystal clock circuit reference.
Fig 10. Prescaler and baud rate generator block diagram
Table 7.
Baud rates using a 1.8432 MHz crystal
Desired baud rate
Divisor used to generate
16
× clock
Percent error difference
between desired and actual
50
2304
0
75
1536
0
110
1047
0.026
134.5
857
0.058
150
768
0
300
384
0
600
192
0
1200
96
0
1800
64
0
2000
58
0.69
2400
48
0
3600
32
0
4800
24
0
7200
16
0
9600
12
0
19200
6
0
38400
3
0
56000
2
2.86
BAUD RATE
GENERATOR
LOGIC
MCR[7] = 1
MCR[7] = 0
PRESCALER
LOGIC
(DIVIDE-BY-1)
INTERNAL
OSCILLATOR
LOGIC
002aaa233
XTAL1
XTAL2
input clock
PRESCALER
LOGIC
(DIVIDE-BY-4)
reference
clock
internal
baud rate
clock for
transmitter
and receiver
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