參數(shù)資料
型號： FIN210ACMLX
廠商： Fairchild Semiconductor
文件頁數(shù)： 9/17頁
文件大?。?/td> 0K
描述： IC SER/DES 10BIT 32-MLP
標(biāo)準(zhǔn)包裝： 3,000
功能： 串行器/解串器
輸入類型： LVCMOS
輸出類型： 串行
輸入數(shù)： 10
輸出數(shù)： 1
電源電壓： 1.65 V ~ 3.6 V
工作溫度： -30°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 32-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 32-MLP（5x5）
包裝： 帶卷 (TR)
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SC1
6
IS7
41_1
NXP
B.V
.
2010.
Al
lr
ig
h
ts
re
s
e
rv
ed.
Produ
ct
d
a
ta
sheet
Rev
.0
1
—
29
Ap
ril
2010
17
o
f52
N
X
P
Semi
conductor
s
SC16IS741
Single
UA
RT
with
I 2
C-
bus
/SPI
in
ter
fa
ce,
64-
by
te
FIFOs,
IrDA
SIR
Table 10.
SC16IS741 internal registers
Register
address
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
General register set[1]
0x00
RHR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R
0x00
THR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
W
0x01
IER
CTS
interrupt
enable[2]
RTS interrupt
enable[2]
Xoff[2]
Sleep mode[2]
modem status
interrupt
receive line
status interrupt
THR empty
interrupt
RX data
available
interrupt
R/W
0x02
FCR
RX trigger
level (MSB)
RX trigger
level (LSB)
TX trigger
level (MSB)[2]
TX trigger
level (LSB)[2]
reserved[3]
TX FIFO
reset[4]
RX FIFO
FIFO enable
W
0x02
IIR[5]
FIFO enable
interrupt
priority bit 4[2]
interrupt
priority bit 3[2]
interrupt
priority bit 2
interrupt
priority bit 1
interrupt
priority bit 0
interrupt status
R
0x03
LCR
Divisor Latch
Enable
set break
set parity
even parity
parity enable
stop bit
word length
bit 1
word length
bit 0
R/W
0x04
MCR
clock
divisor[2]
IrDA mode
enable[2]
Xon Any[2]
loopback
enable
reserved[3]
TCR and TLR
enable[2]
RTS
R/W
0x05
LSR
FIFO data
error
THR and
TSR empty
THR empty
break interrupt framing error
parity error
overrun error
data in receiver R
0x06
MSR
0
CTS
0
ΔCTS
R
0x07
SPR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
0x06
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
0x07
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
0x08
TXLVL
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R
0x09
RXLVL
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R
0x0D
reserved[3]
reserved[3]
reserved[3]
reserved[3]
reserved[3]
0x0E
UART reset reserved[3]
reserved[3]
UART
software reset
reserved[3]
R/W
0x0F
EFCR
IrDA mode
reserved[3]
auto RS-485
RTS output
inversion
auto RS-485
RTS direction
control
reserved[3]
transmitter
disable
receiver
disable
9-bit mode
enable
R/W
Special register set[7]
0x00
DLL
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
0x01
DLH
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
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