參數(shù)資料
型號: FIN224CMLX
廠商: Fairchild Semiconductor
文件頁數(shù): 2/9頁
文件大小: 0K
描述: IC SER/DES 24-BIT BIDIR 40-MLP
標(biāo)準(zhǔn)包裝: 3,000
功能: 串行器/解串器
輸入類型: LVCMOS
輸出類型: 串行
輸入數(shù): 24
輸出數(shù): 1
電源電壓: 1.65 V ~ 3.6 V
工作溫度: *
安裝類型: 表面貼裝
封裝/外殼: 40-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 40-MLP(6x6)
包裝: 帶卷 (TR)
2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FIN224C Rev. 1.0.9
2
SerD
es
FIN
224C
24-
B
it
Low-
P
ower
Serializer/D
eserializer
Pin Configuration
Pin Name
Description
STROBE
LVCMOS Strobe Signal for Latching Data into the Serializer (On Rising Edge)
CKREF
LVCMOS Clock Input and PLL Reference
CKP
LVCMOS Word Clock Output
DP[24:1]
LVCMOS Data I/O
/DIRO
LVCMOS Control Output Inversion of DIRI
S1, S2
LVCMOS Select Pins, Controls the Mode of Operation, see Table 1
DIRI
LVCMOS Control, Selects Serializer or Deserializer Mode
0 Deserializer
1 Serializer
DSO+ / DSI-
DSO- / DSI+
Serial Data I/O
CKSI+, CKSI-
Serial Clock Input
CKSO+, CKSO-
Serial Clock Output
VDDP
Power Supply for Parallel I/O and Internal Circuitry
VDDS
Power Supply for Serial I/O
VDDA
Power Supply for Core
GND
Ground Pins
Note:
1.
0 = VIL; 1 = VIH.
13
14
15
16
17
39
38
36
35
34
33
GND PAD
Must be Grounded
DP[9]
/DIRO
CKSO+
CKSO-
DSO+ / DSI-
DSO- / DSI+
CKSI-
CKSI+
DP
[8
]
DP
[7
]
DP
[6
]
DP
[5
]
DP
[4
]
DP
[3
]
DP[2]
DP
[1
]
DP
[1
9]
DP[20
]
DP
[2
1]
DP[22
]
DP
[2
3]
DP
[2
4]
1
DP[10] 2
4
DP[11]
DP[12]
3
VDDP 5
CKP 6
DP[13] 7
DP[14] 8
12
DP[18
]
11
DP[17
]
40
26
27
25
29
24
18
23
28
30
37
DP[15] 9
DP[16] 10
S2
VDDS
22
21
19
20
32
31
S1
V
DDA
DIRI
STR
O
B
E
CK
R
E
F
13
14
15
16
17
39
38
36
35
34
33
GND PAD
Must be Grounded
DP[9]
/DIRO
CKSO+
CKSO-
DSO+ / DSI-
DSO- / DSI+
CKSI-
CKSI+
DP
[8
]
DP
[7
]
DP
[6
]
DP
[5
]
DP
[4
]
DP
[3
]
DP[2]
DP
[1
]
DP
[1
9]
DP[20
]
DP
[2
1]
DP[22
]
DP
[2
3]
DP
[2
4]
1
DP[10] 2
4
DP[11]
DP[12]
3
VDDP 5
CKP 6
DP[13] 7
DP[14] 8
12
DP[18
]
11
DP[17
]
40
26
27
25
29
24
18
23
28
30
37
DP[15] 9
DP[16] 10
S2
VDDS
22
21
19
20
32
31
S1
V
DDA
DIRI
STR
O
B
E
CK
R
E
F
Figure 2. MLP-40 Pinout (Through View)
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