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參數(shù)資料
| 型號(hào)： | FIN324CGFX |
| 廠商： | Fairchild Semiconductor |
| 文件頁數(shù)： | 9/19頁 |
| 文件大小： | 0K |
| 描述： | IC SER DES 24BIT ULP 42-BGA |
| 產(chǎn)品變化通告： | Mold Compound Change 09/May/2007 Design/Process Change 07/May/2007 |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 系列： | SerDes™ |
| 功能： | 串行器/解串器 |
| 輸入類型： | LVCMOS |
| 輸出類型： | LVCMOS |
| 輸入數(shù)： | 24 |
| 輸出數(shù)： | 24 |
| 電源電壓： | 1.6 V ~ 3 V |
| 工作溫度： | -30°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 42-VFBGA |
| 供應(yīng)商設(shè)備封裝： | 42-BGA |
| 包裝： | 帶卷 (TR) |
2006 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FIN324C Rev. 1.1.4
17
SerDes
FIN324C
—
24-Bit
Ultra-Low
Power
Serializer
/
Deserializer
Supporting
Single
and
Dual
Displays
Physical Dimensions
NOTES:
A. CONFORMS TO JEDEC REGISTRATION MO-220, VARIATION
WJJD-2 WITH EXCEPTION THAT THIS IS A SAWN VERSION..
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M-1994.
D. LAND PATTERN PER IPC SM-782.
E. WIDTH REDUCED TO AVOID SOLDER BRIDGING.
F. DIMENSIONS ARE NOT INCLUSIVE OF BURRS, MOLD FLASH, OR
TIE BAR PROTRUSIONS.
G. DRAWING FILENAME: MKT-MLP40Arev3.
6.00
0.80 MAX
0.10 C
SEATING
PLANE
0.08 C 0.05
0.00
(0.20)
C
0.15 C
PIN #1 IDENT
0.50
4.20
4.00
0.50
0.30
4.20
4.00
0.50
0.10
CA B
0.05
C
0.18-0.30
A
B
6.38MIN
0.20MIN
4.77MIN
4.37MAX
0.28 MAX
0.50TYP
(0.80)
X4
X40
E
(DATUM A)
(DATUM B)
PIN #1 ID
Figure 20.
40-Lead, Molded Leadless Package (MLP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
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