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參數(shù)資料
| 型號： | FIN425CMLX |
| 廠商： | Fairchild Semiconductor |
| 文件頁數(shù)： | 3/10頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SERIALIZER 20BIT 32-MLP |
| 標準包裝： | 3,000 |
| 功能： | 解串器 |
| 輸入類型： | 串行 |
| 輸出類型： | LVCMOS |
| 輸入數(shù)： | 1 |
| 輸出數(shù)： | 20 |
| 電源電壓： | 1.6 V ~ 3 V |
| 工作溫度： | -30°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-MLP（5x5） |
| 包裝： | 帶卷 (TR) |
2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FIN424C / FIN425C Rev. 1.0.0
2
SerD
es
FIN
4
24C
/
FIN
425C
—
20-
B
it
U
lt
ra-
Low-
P
ower
Serializer
/
D
eserializer
f
o
rC
ont
roller
and
R
G
B
D
isplays
FIN424C Serializer Pin Descriptions
Pin Name
Description
STRB
LVCMOS Strobe Signal for Latching Data into the Serializer (On Rising Edge)
DP[19:0]
LVCMOS Data Input
/RES
Low-Power Mode
0 Serializer Low Power
1 Serializer Enabled
/STBY
SerDes Standby
0 Serializer and Deserializer in Low Power
1 Serializer and Deserializer Enabled
Test
Internal Use (Should be GND)
DS+, DS-
Serial Data Output
CKS+, CKS-
Serial Clock Output
VDDP
Power Supply for Parallel I/O and Internal Circuitry
VDDS
Power Supply for Serial I/O
VDDA
Power Supply for Core
GND
Ground Pins
Notes:
1.
0 = VIL; 1 = VIH.
2.
All GND and VDDP pins must be connected to ground and VDDP, respectively.
11
12
13
14
15
31
30
28
27
26
25
GND PAD
Must be Grounded
CKS+
DP[12]
DP[11]
DP[10]
VDDP
DP[9]
DP[8]
DP[7]
DP[6]
DP[
1
9]
DP[
1
8]
DP[
1
7]
DP[
1
6]
DP[
1
5]
ST
R
B
DP[
1
4]
DP[
1
3]
DP
[0
]
DP
[1
]
DP
[2
]
DP
[3
]
DP
[4
]
DP
[5
]
1
CKS- 2
4
VDDS
VDDA
3
DS- 5
DS+ 6
/RES 7
VDDP 8
10
Te
st
9
/ST
B
Y
32
20
21
19
23
18
16
17
22
24
29
11
12
13
14
15
31
30
28
27
26
25
GND PAD
Must be Grounded
CKS+
DP[12]
DP[11]
DP[10]
VDDP
DP[9]
DP[8]
DP[7]
DP[6]
DP[
1
9]
DP[
1
8]
DP[
1
7]
DP[
1
6]
DP[
1
5]
ST
R
B
DP[
1
4]
DP[
1
3]
DP
[0
]
DP
[1
]
DP
[2
]
DP
[3
]
DP
[4
]
DP
[5
]
1
CKS- 2
4
VDDS
VDDA
3
DS- 5
DS+ 6
/RES 7
VDDP 8
10
Te
st
9
/ST
B
Y
32
20
21
19
23
18
16
17
22
24
29
Figure 2.
FIN424CMLX MLP-32 Pinout (Top Through View)
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