參數(shù)資料
型號(hào): FM24CL64-S
廠商: Electronic Theatre Controls, Inc.
元件分類: DRAM
英文描述: 4Kb FRAM Serial 3V Memory
中文描述: 4Kb的鐵電串行3V的記憶
文件頁數(shù): 9/11頁
文件大小: 77K
代理商: FM24CL64-S
Ramtron
FM24CL64
9 May 2001
9/9
AC Parameters
TA = -40
°
C to + 85
°
C, VDD =2.7V to 3.65V unless otherwise specified
Symbol Parameter
f
SCL
SCL Clock Frequency
t
LOW
Clock Low Period
t
HIGH
Clock High Period
t
AA
SCL Low to SDA Data Out Valid
Min
0
4.7
4.0
Max
100
3
Min
0
1.3
0.6
Max
400
0.9
Min
0
0.6
0.4
Max
1000
0.55
Units
kHz
μ
s
μ
s
μ
s
Notes
1
t
BUF
Bus Free Before New
Transmission
Start Condition Hold Time
Start Condition Setup for Repeated
Start
Data In Hold
Data In Setup
Input Rise Time
Input Fall Time
Stop Condition Setup
Data Output Hold
(from SCL @ VIL)
Noise Suppression Time Constant
on SCL, SDA
4.7
1.3
0.5
μ
s
t
HD:STA
t
SU:STA
4.0
4.7
0.6
0.6
0.25
0.25
μ
s
μ
s
t
HD:DAT
t
SU:DAT
t
R
t
F
t
SU:STO
t
DH
0
250
4.0
0
1000
300
0
100
0.6
0
300
300
0
100
0.25
0
300
100
ns
ns
ns
ns
μ
s
ns
2
2
t
SP
50
50
50
ns
Notes : All SCL specifications as well as start and stop conditions apply to both read and write operations.
1
The speed-related specifications are guaranteed characteristic points along a continuous curve of operation from
D.C. to 1 MHz.
2
This parameter is periodically sampled and not 100% tested.
Capacitance
TA = 25
°
C, f=1.0 MHz, VDD = 3V
Symbol
Parameter
Max
C
I/O
Input/output capacitance (SDA)
8
C
IN
Input capacitance
6
Notes
1
This parameter is periodically sampled and not 100% tested.
AC Test Conditions
Input Pulse Levels
VDD * 0.1 to VDD * 0.9
Input rise and fall times
10 ns
Input and output timing levels
VDD*0.5
Equivalent AC Load Circuit
Units
pF
pF
Notes
1
1
3.65V
Output
1100
100 pF
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