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參數(shù)資料
| 型號： | FM3580MT20 |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2mm TERMINAL STRIP |
| 中文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PDSO20 |
| 封裝： | TSSOP-20 |
| 文件頁數(shù)： | 2/11頁 |
| 文件大?。?/td> | 107K |
| 代理商： | FM3580MT20 |
2
F
www.fairchildsemi.com
FM3580 Rev. A.5
20-Pin TSSOP
SCL
SDA
/OVERRIDE
I0
I1
I2
I3
I4
LEVEL
GND
VCC
ASEL
WP
Non_Mux_Out
Mux_Sel
Y0
Y1
Y2
Y3
Y4
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Part Number
Package Number
Package Description
FM3580MT20
MT20
20-Pin TSSOP
Note:
For other package options please consult Fairchild Sales/Marketing.
Pin Connection Diagram
Pin Description
Pin Name
Description
I[0:4]
Input data. These 5 signals have internal pullup (10K
to 40K
).
Y[0:4]
Multiplexed Output data signals.
SCL
Serial Clock Input for SMBus access. has an internal pullup (125K
).
SDA
Serial Data Input/Output for SMBus access. As an internal pullup (125K
).
/OVERRIDE
Active low input to select Y-port output data. See Table 1.
Level
Output level select input. When low, the Y[0:4] outputs are driven up to 2.5V and the Non_Mux_Out signal is
driven up to V
CC
; When high, the Y[0:4] outputs and the Non_Mux_Out signal operate as an Open-Drain type.
This signal has an internal pullup resistor and can be left unconnected for Open-Drain type Y[0:4] outputs and
Non_Mux_Out signal.
ASEL
Address select input. When set high, the device will respond to 1001-110 7-bit address and when set low,
the device will respond to 0110-111 7-bit address.
WP
Write Protect input. When set high, prevents writes to internal registers.
Non_Mux_Out
Non-Multiplexed output.
Mux_Sel
Multiplexer select input to select Y-port output data. See Table 1.
V
CC
Power input to the device.
GND
Ground.
Ordering Code
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