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參數資料
| 型號： | FM3580MT20 |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2mm TERMINAL STRIP |
| 中文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PDSO20 |
| 封裝： | TSSOP-20 |
| 文件頁數： | 6/11頁 |
| 文件大小： | 107K |
| 代理商： | FM3580MT20 |
6
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www.fairchildsemi.com
FM3580 Rev. A.5
Functional Description
Legacy VID Operation
During standard operation FM3580 (the device) will pass data
from the I[0:4] inputs (I-Port) or data from an internal register
SOPR-A or data from an internal register SOPR-B to the Y[0:4]
outputs (Y-Port). Logic is implemented through a set of multiplex-
ers. All the signals and the control involved in the VID operation
are explained below.
Output Port (Y-Port): Y[0-4]
This Y-Port output forms the power management signals to
determine the CPU power level and is typically connected to the
motherboard DC-DC converter. As mentioned before this Y-Port
is a multiplexed output of either the I-Port input or data from one
of the two internal registers (SOPR-A ; SOPR-B). Choice of which
one is selected is determined by Mux_Sel input signal and
Bits[7:6] of SOPR-A/SOPR-B registers. Note that Bit7 and Bit 6
are defined to be common for both SOPR-A and SOPR-B regis-
ters. Rest of the bits (Bit5:0) are defined to be separate.
At power up the default path is from I-Port to Y-Port till a valid
SMBus write command is issued to set Bits[7:6] at which point the
Y-Port output is determined by the combined status of Mux_Sel
input signal and the Bit[7:6] values. The multiplexer only updates
when an SMBus stop condition is observed. The output type of the
Y-Port can be configured for either an Open-drain type or TTL type
using Level input. Y-Port is always active. Refer Multiplexer Block
diagram. Table.1 summarizes above description.
Input Port (I-Port): I[0-4]
The I-port values are generated externally on the PC motherboard
and may be either hardwired or driven by another device. Internal
pull-up resistors are provided on the I-Port to accommodate this
device being driven by an open-drain output driver.
Level Input
This input controls the output type of the Y-Port signals and
Non_Mux_Out signal. If Level signal is connected to Ground, then
the Y-Port outputs are actively driven to 2.5V and Non_Mux_Out
signal is actively driven up to V
CC
. If Level signal is connected to
V
(or left unconnected), then the Y-Port signals and
Non_Mux_Out signal operate as open-drain outputs. Level input
has an internal pull-up resistor and hence can be left unconnected
to recognize a logic high at its input.
Non_Mux_Out Output
This is an output signal and it reflects the Bit4 of either SOPR-A or
SOPR-B register. Like the Y-Port, Bit[7:6] values determine the
selection of either Bit 4 of SOPR-A or Bit4 of SOPR-B register. The
Non_Mux_Out output is transparent when the Mux_sel signal is at
logic 0 and will latch data on the rising edge of the Mux_sel signal.
Mux_Sel Input
This is an input signal and is used to select data for Y-Port outputs.
If this signal is set to logic 1, I-Port data is driven on the Y-Port and
when set to logic 0 (and /Override = 1), data from one of the two
internal non-volatile registers (SOPR-A or SOPR-B) are driven on
the Y0-4 outputs.
/Override Input
This is an input signal and when set to logic low (and Mux_Sel =
0), will cause all the Y-Port outputs and Non_Mux_Out output to
be set to Logic Low.
VID Registers Description
FM3580 has 3 internal registers, viz. SOPR-A, SOPR-B and PIPR
for VID function. These registers are made up of a combination of
read-only, write-only and read-write bits.
Serial Output Port Register A (SOPR -A)
This is a 8-bit read-write register that contains 5-bit data for output
Y-Port, 1-bit data for Non_Mux_Out Output and two multiplexer
select bits. This register can be read and written through SMBus
and is at address 0x00h. Refer SOPR-A/B diagram.
Serial Output Port Register B (SOPR -B)
This is a 8-bit read-write register that contains 5-bit data for output
Y-Port, 1-bit data for Non_Mux_Out Output and two multiplexer
select bits. This register can be read and written through SMBus
and is at address 0x01h. Refer SOPR-A/B diagram.
Parallel Input Port Register (PIPR)
This is a 8-bit read-only register. Bits[7:5] are reserved and are set
to read
“
0
”
always. Bits[4:0] contain latched I-Port value. I-port
data is latched into this register on the first clock after a
“
START
”
condition is detected on the SMBus. This insures valid value be
read from this register always. This register can only be read
through SMBus and is at address 0x02h. Refer PIPR diagram.
SMBus Interface
FM3580 uses standard SMBus protocol to communicate with external
interface (system). Various blocks and features of this device are
accessible through the SMBus interface. This device supports both
byte and block reads as defined in the SMBus specification. VID block
is accessed through byte-write and block-read commands, while the
Security block is accessed through block-read/write commands.
Device Addressing
FM3580 uses 7 bit SMBus addressing. If the ASEL input is
‘
1,
’
then
the device will respond to 1001-110 address. If the ASEL input is
‘
0,
’
then the device will respond to 0110-111 address. The address
byte is the first byte of data sent after a start condition. The device
will not respond to the general call address 0000-000.
SOPR-A Register Write Operation (Byte)
Following is the SMBus command sequence to write SOPR-A
register. Write operation starts with a valid
“
START
”
command,
followed by device address byte with Read-Write bit set to
“
0.
”
On
receiving a valid device address, FM3580 issues an
“
ACK
”
pulse.
This is followed by register address byte (0x00h) to select the
SOPR-A register. On receiving this register address byte, FM3580
issues an
“
ACK
”
pulse. This is followed by data byte to be written
into the SOPR-A register. On receiving this data byte, FM3580
issues an
“
ACK
”
pulse. This is followed by a
“
STOP
”
command at
which point write operation begins internally. Refer Write VID
Registers diagram.
SOPR-B Register Write Operation (Byte)
Write sequence to SOPR-B register is same as the SOPR-A
register write sequence described above except instead of 0x00h
value for register address, 0x01h should be used. This will select
SOPR-B register. Refer Write VID Registers diagram.
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