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參數(shù)資料
| 型號(hào)： | FM3808DK |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | DRAM |
| 英文描述： | 4Kb FRAM Serial 3V Memory |
| 中文描述： | 4Kb的鐵電串行3V的記憶 |
| 文件頁數(shù)： | 2/28頁 |
| 文件大?。?/td> | 191K |
| 代理商： | FM3808DK |
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FM3808
Rev 1.1
May 2003
Page 2 of 28
FRAM Array
32,752x8
Address Decoder/
Bus Interface
16 Clock/Calendar
Registers
Clock/Calendar
Alarm
Interrupt Control
Logic
System Supervisor
Low VDD monitor/
Watchdog timer
Data
Address
CE
OE
WE
INT
32.768
kHz
VDD
VBAK
Switched
power
Watchdog
timebase
X1
X2
Figure 1. Block Diagram
Pin Description
Pin Name
A0-A14
I/O
Input
Pin Description
Address: The 15 address inputs select one of 32,752 bytes in the FRAM array or one of
16 bytes in the clock/calendar. The address is latched on the falling edge of /CE.
Data: Bi-directional 8-bit data bus for accessing the FRAM array and clock.
Chip Enable: The active low /CE input selects the device. The falling edge of /CE
internally latches the address. Address changes that occur after /CE has transitioned
low are ignored until the next falling edge occurs.
Output Enable: The active low /OE input enables the data output buffers during read
cycles. Deasserting /OE high causes the DQ pins to tri-state.
Write Enable: The active low /WE low enables data on the DQ pins to be written to the
address location latched by the falling edge of /CE.
Connect 32.768 kHz crystal.
Interrupt output: This output can be programmed to respond to the clock/calendar
alarm, the watchdog timer, and the power monitor. It is programmable to either active
high (push/pull) or active low (open-drain).
Backup Supply Voltage: This supply is used to maintain power for the clock. It must
remain between 2.5V and V
DD
-0.3V. V
BAK
is typically supplied by either a capacitor
or a battery. Current is drawn from V
BAK
when V
DD
is below the V
BAK
voltage.
Supply Voltage: 5V
Ground.
DQ(7:0)
/CE
I/O
Input
/OE
Input
/WE
Input
X1, X2
INT
Input
Output
V
BAK
Supply
V
DD
V
SS
Supply
Supply
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