FM3808
Rev 1.1
May 2003
Page 20 of 28
Electrical Specifications
Absolute Maximum Ratings
Symbol
V
DD
V
IN
Description
Ratings
-1.0V to +7.0V
-1.0V to +7.0V and
V
IN
< V
DD
+1.0V
-55
°
C to + 125
°
C
300
°
C
Power Supply Voltage with respect to V
SS
Voltage on any signal pin with respect to V
SS
T
STG
T
LEAD
Storage temperature
Lead temperature (Soldering, 10 seconds)
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.
This is a stress rating only, and the functional operation of the device at these or any other conditions above
those listed in the operational section of this specification is not implied. Exposure to absolute maximum
ratings conditions for extended periods may affect device reliability.
DC Operating Conditions
(T
A
= -40
°
C to + 85
°
C, V
DD
= 4.5V to 5.5V unless otherwise specified)
Symbol
Parameter
V
DD
Power Supply Voltage
I
DD
V
DD
Supply Current – Active
I
SB1
Standby Current – TTL
I
SB2
Standby Current – CMOS
V
BAK
Clock Backup Voltage
I
BAK
Clock backup current
V
TP
V
DD
trip point voltage that activates INT pin
V
LO
V
DD
Lockout Voltage
V
SW
V
DD
Voltage that causes switch to V
BAK
V
RST
V
DD
Voltage for Active INT pin
I
LI
Input Leakage Current
I
LO
Output Leakage Current
V
IH
Input High Voltage
V
IL
Input Low Voltage
V
OH
Output High Voltage (I
OH
= -2.0mA)
V
OL
Output Low Voltage (I
OL
= 4.2mA)
V
OLB
Output Low Voltage (INT pin)
Device in backup mode (V
DD
<V
BAK
)
Notes
1.
V
DD
= 5.5V, /CE cycling at minimum cycle time. All inputs at CMOS levels, all outputs unloaded.
2.
V
DD
= 5.5V, /CE at V
IH
, All other inputs and DQ pins at TTL levels.
3.
V
DD
= 5.5V, /CE at V
IH
, All other inputs and DQ pins at CMOS levels.
4.
V
BAK
= 3.0V, V
DD
< V
BAK
; oscillator running. This parameter is characterized, not 100% tested.
5.
V
SW
occurs when V
DD
drops below V
BAK
. V
SW
is also the point at which the timekeeper draws current from the V
BAK
pin,
rather than from V
DD
. V
SW
is not otherwise used for control signals or functions.
6.
INT pin conditions are I
OL
= 80 uA and V
OL
= 0.4V.
7.
V
IN
, V
OUT
between V
DD
and V
SS
.
8.
Memory and register access is blocked when V
DD
< V
LO
.
9.
V
DD
=0, V
BAK
= 3.0V, I
OL
= 4.2 mA.
Min
4.5
2.5
4.35
4.2
1.2
2.0
-0.5
2.4
Typ
5.0
10
3.0
V
BAK
Max
5.5
25
500
150
V
DD
1
4.65
4.49
10
10
V
DD
+ 0.5
0.8
0.4
0.7
Units
V
mA
μ
A
μ
A
V
μ
A
V
V
V
V
μ
A
μ
A
V
V
V
V
V
Notes
1
2
3
4
8
5
6
7
7
9