PRODUCT SPECIFICATION
FMS2704/FMS2704L
22
REV. 1.01 12/2/99
Otherwise INT = Z, open drain. Figure 6 depicts the logical
ow of the interrupt sources to the INT output.
For the Tachometer Status Register, if any one of the six fan
speed inputs violates the speed boundary, the appropriate
ERRORA1-3,B1-3 bit is set. Unused tachometer inputs can be
disabled by programming in the Tachometer Conguration
Register. Unwanted interrupts can be masked by program-
ming the Tachometer Mask Register.
Voltage Status Register bits indicate if any one of the six volt-
meter inputs violates the high or low voltage trip levels bound-
ary, causing the appropriate ERROR_V6-1 bit to be set.
Unwanted interrupts can be masked by programming the Volt-
meter Mask Register.
Figure 6. INT Output Structure
Interrupt
Status
Register
LTV & RTV
Interrupt
Control &
Masking
Interrupt
Status
Register
Mirror
THERM
ITHERM
XTHERM
Mask
Gating
INT
Interrupt
Mask
Register(s)
THERM,
FAULT1-2
Configuration
Register
Interrupt
Control
INT_EN
INT_CLR
SOFT_RST
INT_RST
LTV, RTV2-1
ERROR_V6-1
ERROR_TA3-1,B3-1
FAULT_D1-2
With Conguration Register bits INT_EN = 1 and INT_CLR
= 0, output pin INT = L, if any of the following bits are set in
the Temperature Interrupt Register:
1.
LTV: An local temperature limit is violated indicating
that the on-chip temperature falls outside the boundaries
established by TLLO7-0 and TLHI7-0.
2.
RTV1: Remote thermal diode 1 temperature limit is
violated, indicating that the temperature falls outside the
boundaries established by TRLO7-0 and TRHI7-0.
3.
RTV2: Remote thermal diode 2 temperature limit is
violated, indicating that the temperature falls outside the
boundaries established by TRLO7-0 and TRHI7-0.
4.
THERM: Temperature exceeds an selected automatic
trip point (PTL7-0, PTR7-0, FTL7-0, or FTR7-0) causing
output THERM = L or the THERM input = L even if the
THERM bit in the Interrupt Register is masked.
5.
FAULT_D1-2: Remote diode D1-2 is either open or short
circuit.
Output pin INT = Z, clearing the interrupt output, if any of the
following events occur:
1.
Interrupt Status Register is read, causing this register to
be cleared to the default state that is all interrupts
cleared. However a THERM or FAULT1-2 condition will
cause an immediate re-assertion of the interrupt.
2.
Conguration Register bit INT_CLR = 1, which is the
default condition following an internal reset.
3.
Conguration Register bit INT_EN = 0, which is the
default condition following an internal reset.
Status of the INT_CLR and INT_EN bits does not impact the
contents of the Interrupt Status. Reading the Interrupt Status
Registers clears only that register.
Note that setting the INT output by exceeding a temperature
limit is an edge-driven event. Only when the temperature
actually crosses the limit boundary does INT transition LOW.
An example of interrupts caused by a series of temperature, T
transitions across temperature limits is shown in Figure 7.