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參數(shù)資料
| 型號： | fp_add_sub |
| 廠商： | Altera Corporation |
| 英文描述： | Floating-Point Adder/Subtractor(浮點(diǎn)型加法器/減法器) |
| 中文描述： | 浮點(diǎn)加法器/減法（浮點(diǎn)型加法器/減法器） |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 132K |
| 代理商： | FP_ADD_SUB |
Altera Corporation
5
FS 2: fp_add_sub Floating-Point Adder/Subtractor
Example 3: Negative Number Plus Insignificant Positive Number
–0.5
×
2
89
–0.10000000
×
2
89
+ +0.10000000
×
2
68
–0.10000000
×
2
89
+ +0.00000000
×
2
89
–0.10000000
×
2
89
–0.5
×
2
89
+ +0.5
×
2
68
=
=
=
=
In example 3, the result is the same as the larger input value because
0.5
×
2
68
is insignificant compared to –0.5
×
2
89
.
Floating-Point
Representation
Floating-point numbers can be represented by many different notations.
The
fp_add_sub
function uses an implied leading zero for the mantissa,
with an unsigned,
m
-bit mantissa and
n
-bit exponent, where
m
=
mantissa_width
and
n
=
exponent_width
. A separate sign bit is
used to represent the sign of the mantissa.
The following examples of an 8-bit positive mantissa and a 7-bit exponent
assume
mantissa_width
= 8 and
exponent_width
= 7. The numbers
shown in
Table 3
below should be adjusted accordingly if different
parameter values are used.
An 8-bit positive mantissa allows fractions with numerators between 0
and 255. The implied leading zero limits the range of the mantissa
between 0 and 0.9961, and the separate sign bit allows the mantissa to
have a value between –0.9961 and +0.9961. Because the mantissa is in
fractional form, a greater number of bits in the mantissa does not result in
a larger mantissa, but offers greater precision.
Table 3
lists examples of
8-bit mantissas with implied leading zeros.
Table 3. 8-Bit Mantissa Examples
Mantissa
Implied Zero
Binary Fraction
Decimal
Fraction
Decimal
11001110
00001100
10100001
0.11001110
0.00001100
0.10100001
11001110 / 100000000
00001100 / 100000000
10100001 / 100000000
206 / 256
12 / 256
161 / 256
0.80469
0.04688
0.62891
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