MB91360G Series
118
16. BUS INTERFACE
The external bus interface controls the interfaces with the external memory and external I/Os.
Up to 32-bit (4 GB) address output.
Up to eight independent banks provided by chip-select function
The banks can be set in 64-KB (minimum) at any position in the logic address space.
Can be set to no area
32/16/8 bit bus width setup can be performed for each chip-select area.
Programmable automatic memory wait (up to 7 cycles) insertion
Unused address/data pins can be used as I/O ports. (But see notes below)
Note : Chip Select Area CS7 is used for the internal CAN modules. The necessary register settings are done by
an internal boot routine. Take care not to overwrite register bits related to this CS area.
If the CAN macros which are connected internally to the external bus (also called User Logic Bus) are used,
a certain number of data, address and control ports of the external bus interface cannot be configured as
general purpose IO ports.
(1) Register Configuration
(Continued)
Area select Registers
(
ASR0
to
ASR7
)
After execution of the code in the initial boot ROM ASR0 is set to “0x20”, and ASR7 to “0x10”.
ASR0
Initial value
INIT
0000
H
Initial value
INIT
0000
H
Initial value
INIT
0000
H
Initial value
INIT
0000
H
Initial value
INIT
0000
H
Initial value
INIT
0000
H
Initial value
INIT
0000
H
Access
RST
0000
H
00000640
H
W
ASR1
Access
RST
XXXX
H
00000644
H
W
ASR2
Access
RST
XXXX
H
00000648
H
W
ASR3
Access
RST
XXXX
H
0000064C
H
W
ASR4
Access
RST
XXXX
H
0000650
H
W
ASR5
Access
RST
XXXX
H
00000654
H
W
ASR6
Access
RST
XXXX
H
00000658
H
W
ASR7
Initial value
INIT
0000
H
Access
RST
XXXX
H
0000065C
H
W
15
14
13
12
2
1
0
A30
A31
A29
PO4
PO3
A18
A17
A16
. . .
15
14
13
12
2
1
0
A30
A31
A29
PO4
PO3
A18
A17
A16
. . .
15
14
13
12
2
1
0
A30
A31
A29
PO4
PO3
A18
A17
A16
. . .
15
14
13
12
2
1
0
A30
A31
A29
PO4
PO3
A18
A17
A16
. . .
15
14
13
12
2
1
0
A30
A31
A29
PO4
PO3
A18
A17
A16
. . .
15
14
13
12
2
1
0
A30
A31
A29
PO4
PO3
A18
A17
A16
. . .
15
14
13
12
2
1
0
A30
A31
A29
PO4
PO3
A18
A17
A16
. . .
15
14
13
12
2
1
0
A30
A31
A29
PO4
PO3
A18
A17
A16
. . .