參數(shù)資料
型號(hào)： FS450AC
廠商： Electronic Theatre Controls, Inc.
英文描述： i-Net TV Interface Video Processor
中文描述： 一至網(wǎng)絡(luò)電視接口視頻處理器
文件頁(yè)數(shù)： 23/60頁(yè)
文件大?。?/td> 266K
代理商： FS450AC
FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
JUNE, 2000, VERSION 1.2
23
COPYRIGHT
ó
1999,2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORMATION
6.2.6 CR - Command Register
Command Register (C)
7
6
5
4
3
2
1
0
FFO_CLR
CACQ_CLR
LP_EN
YCOFF
COMPOFF
NCO_EN
CLKOFF
SRESET
Command Register (D)
7
6
5
4
3
2
1
0
UIM_MOD
1
UIM_MOD
0
0
UIM_DEC
UIM_CLK
OFMT
STD_VMI
NTSC_PALIN
Reg
Bit#
Bit Name
Description
C
0
SRESET
Soft Reset.
Resets the FS450.
C
1
CLKOFF
Clock Off.
Turns off FS450 clock to minimize power.
C
2
NCO_EN
Enable NCO Latch.
When this bit is set, transfers the NCO
words from the I2C registers into the NCO. The NCO synthesizes
the VGA clock from the 27MHz FS450 clock. This clock must be
adjusted so the VGA scaled input data rate exactly matches the
CCIR 656 data output rate.
C
3
COMPOFF
Composite (CVBS) Output Off.
Turns off the CVBS output D/A.
C
4
YCOFF
SVideo (YC) Outputs Off.
Turns off the YC output D/As.
C
5
LP_EN
Loop Through Enable.
Enables the CCIR 656 data on the output
port to loop directly to the input port (no external routing).
C
6
CACQ_CLR
Counter Acquisition Flag Clear.
Setting this bit clears the
Counter Acquisition Flag.
C
7
FFO_CLR
FIFO Clear.
Setting this bit clears the FIFO depth registers and
the FIFO State register.
D
0
NTSC_PALIN
CCIR 656 PAL or NTSC Input.
Sets the number of lines written
through the FIFO. When set, the number of lines is 576 for PAL,
when clear, 487 lines for NTSC.
D
1
STD_VMI
Standard or VMI 656 Input Control.
Select standard (external
pins) horizontal/vertical blank and field codes or inserted CCIR
601/656 SAV/EAV (Start/End Active Video) embedded codes.
D
2
OFMT
Output Format Control.
Switches between RGB or
Composite/YC output. When set, the output is RGB.
D
3
UIM_CLK
Universal Interface Mux Clock Mode.
If set, input pixels are
clocked in on the falling edge of the P and N input clocks. If clear,
input pixels are clocked on the rising and falling edge of N clock.
D
4
UIM_DEC
Universal Interface Mux Decimator.
Turns on the horizontal
prescaler divide by 2 to support XGA mode.
D
7,6
UIM_MOD
1-0
Universal Interface Mode Select.
Selects the VGA interface
mode (see table below).
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