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參數(shù)資料
| 型號： | FS450AC |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | i-Net TV Interface Video Processor |
| 中文描述： | 一至網(wǎng)絡(luò)電視接口視頻處理器 |
| 文件頁數(shù)： | 5/60頁 |
| 文件大?。?/td> | 266K |
| 代理商： | FS450AC |
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FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
JUNE, 2000, VERSION 1.2
5
COPYRIGHT
ó
1999,2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORMATION
2. Architectural Overview
The FS450 i-Net TV Video Interface Processor provides NTSC or PAL TV out for Intel's 82810 Video Co-
processor and many other 3D graphic controller ("GCC") chips. It accepts digital RGB in, converts it to
CCIR 656 digital video, provides interfaces to external 656 digital DVD systems, windowing hardware, alpha
blenders, et al and outputs very high quality RGB, YUV, S-Video, or Composite Video. The chip consists of
the following major sections:
Oscillators and PLLs
Serial Control Port
Sync Control
Input and Output Frame Formats
Color Space Converter & Scaler
Encoder
YUV to RGB Converter
U
&
/12
RED
GRN
BLU
RGB
to
YUV
/24
H
/24
V
/16
/16
Flicker
Filter
/32
F
/8
CCIR
656
Out
/16
CCIR
656
In
/8
D
/16
Encoder
YUV
to
RGB
BLU/CHRMA
GRN/CVBS
DAC
DAC
DAC
RED/LUMA
M
/30
/30
/10
/10
/10
Decoder
27 MHz
Clock
NCO
o w
VCO
Divider
CPU
VGA
Clock
Cache
FIFO
H
/24
/32
VGA
Timing
Generator
/3
VSync
HSync
Blank
CCIR 656
Timing
Generator
Auxiliary
HREF
VREF
/2
HBlank In
VBlank In
Field In
/3
HBlank Out
VBlank Out
Field Out
/3
H
Divider
ERED
EGRN
EBLU
/6
Figure 2: FS450 Functional Block Diagram
2.1 Oscillators and PLLs
The FS450 synthesizes a 27 to 85 MHz clock off of the 27 MHz Television clock and supplies this clock
(VGA_CKOUT) to the GCC. This clock is buffered and returned to the FS450 (VGA_CKIN) synchronous to
the RGB data and Sync information. This clock has a 1 Hz resolution and must be adjusted so the GCC
scaled input data rate exactly matches the CCIR 656 data output rate.
The VG_CKOUT Phase Lock Loop (PLL) synthesizer uses Numerically Controlled Oscillator (NCO) to fine
adjust the 27MHz oscillator to a clock precisely matched to the digital RGB data coming from the GCC.
Additionally, the PLL itself can be controlled by programming the numerator (M) and denominator (N) of the
PLL itself. The combination of the PLL synthesizer and NCO are used to precisely match the input to the
output.
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