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參數(shù)資料
| 型號： | FSAR001BNY |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 電源模塊 |
| 英文描述： | AC-DC REG PWR SUPPLY MODULE |
| 封裝： | GREEN, MS-001BA, DIP-8 |
| 文件頁數(shù)： | 12/12頁 |
| 文件大?。?/td> | 494K |
| 代理商： | FSAR001BNY |
2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSAR001 Rev. 1.0.0
9
FSAR001
—
AC-DC
Linear
Regulator
Functional Description (Continued)
EQ 1
t0
t1
t2
Ts/2
Ts
VIN
IIN
VINpeak
VINDET
t
a.
b.
Figure 18. Typical Waveforms
VDD Pin Over-Voltage Protection
After startup, FSAR001 turns on the OVP function.
During conduction angle interval, the VDD voltage has
two kinds of behavior. One is that if the VDD capacitor
recharges to OVP trigger point (8.5V for 5V version),
the FSAR001 turns off the power MOSFET to limit the
maximum VDD voltage. The other is that if the voltage of
VDD cannot recharge to the OVP level during the
conduction interval, the power MOSFET is turned off by
AC synchronous signal and continuously recharges VDD
capacitor at next duration. Using this technique, energy
is drawn from the AC mains only during the low-voltage
portions of each positive half cycle, reducing the
dissipation in the first stage. During the power MOSFET
turn-on, the current provided by the commutated AC
voltage is used to supply the loads and to charge the
VDD capacitor. In this way, when the power MOSFET
switches off, the loads receive the required currents by
the capacitor discharge. For this reason, it is important
to properly set the conduction angle.
For the VDD capacitor selection, during conduction angle
interval; the energy is drawn from commutated AC bus,
which not only provides the output requirement but also
recharges the VDD capacitor to OVP level. Outside of
conduction angle, the VDD capacitor supplies the whole
system requirement. The VDD capacitor can be reduced
by maximum loading power. The capacitor is evaluated
by Equation 2; the selection chart is shown in Figure 19.
)
(
,
1
10
F
unit
m
I
C
LOAD
VDD
=
×
=
EQ 2
0
100
200
300
400
500
600
0
10
2030
4050
Load Current (mA)
V
D
capaci
to
r
(u
F
Figure 19.
VDD Capacitor vs. Output Current
Vac
R
V
Vac
R
V
DET
×
+
=
×
+
=
4
3
4
3
4
min
,
max
,
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