參數(shù)資料
型號: FT2232H MINI MODULE
廠商: FTDI, Future Technology Devices International Ltd
文件頁數(shù): 35/67頁
文件大?。?/td> 0K
描述: MOD USB HS FT2232H EVAL
產品變化通告: Part Number Change Jan 2011
產品目錄繪圖: FT(22, 42)32HQ MINI MOD
標準包裝: 5
主要目的: 接口,USB 2.0 至 UART、JTAG、SPI、I2C
嵌入式:
已用 IC / 零件: FT2232H
主要屬性: 高速,異步串行數(shù)據(jù),300 波特 ~ 12 Mbaud,TTL 級
次要屬性: JTAG、SPI 和 I2C 上同步串行(MPSSE)數(shù)據(jù)傳輸速度高達 30Mbps
已供物品:
產品目錄頁面: 633 (CN2011-ZH PDF)
相關產品: 768-1010-6-ND - IC USB FS DUAL UART/FIFO 48-LQFP
768-1010-1-ND - IC USB FS DUAL UART/FIFO 48-LQFP
768-1010-2-ND - IC USB FS DUAL UART/FIFO 48-LQFP
其它名稱: 768-1030
FT2232HQ_MINI MOD
Copyright 2012 Future Technology Devices International Limited
40
Document No.: FT_000061
FT2232H DUAL HIGH SPEED USB TO MULTIPURPOSE UART/FIFO IC
Version 2.21
Clearance No.: FTDI#77
4.9 CPU-style FIFO Interface Mode Description
CPU-style FIFO interface mode is designed to allow a CPU to interface to USB via the FT2232H. This mode
is enabled in the external EEPROM. The interface is achieved using a chip select bit (CS#) and address bit
(A0). When either Channel A or Channel B are in CPU-style Interface mode the IO signal lines are
configured as given in Table 3.10.
This mode uses a combination of CS# and A0 to determine the operation to be carried out. The following
truth-table, Table 4.7, gives the decode values for particular operations.
CS#
A0
RD#
WR#
1
X
0
Read Data Pipe
Write Data Pipe
0
1
Read Status
Send Immediate
Table 4.7 CPU-Style FIFO Interface Operation Select
The Status read is shown in Table 4.8
Data Bit
Data
Status
bit 0
1
Data available (=RXF)
bit 1
1
Space available (=TXE)
bit 2
1
Suspend
bit 3
1
Configured
bit 4
X
bit 5
X
bit 6
X
bit 7
X
Table 4.8 CPU-Style FIFO Interface Operation Read Status Description
Note that bits 7 to 4 can be arbitrary values and that X= not used.
The timing of reading and writing in this mode is shown in Figure 4.17 and Table 4.9.
CS#
WR#
RD#
A0
Valid
t3
t1
t2
t4
t5
t6
t7
D7..0
Figure 4.17 CPU-Style FIFO Interface Operation Signal Waveforms.
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