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參數(shù)資料
| 型號(hào)： | FW801A-DB |
| 英文描述： | Low-Power PHY IEEE 1394A-2000 One-Cable Transceiver/Arbiter Device |
| 中文描述： | 低功耗PHY的IEEE 1394A端口，2000年一電纜收發(fā)器/仲裁器裝置 |
| 文件頁數(shù)： | 8/24頁 |
| 文件大?。?/td> | 378K |
| 代理商： | FW801A-DB |
8
Agere Systems Inc.
FW801A Low-Power PHY
IEEE
1394A-2000
One-Cable Transceiver/Arbiter Device
Data Sheet, Rev. 1
June 2001
Signal Information
(continued)
Table 1. Signal Descriptions
(continued)
* Active-low signals are indicated by “/” at the beginning of signal names, within this document.
Pin
Signal
*
Type
Name/Description
14
LPS
I
Link Power Status.
LPS is connected to either the V
DD
supplying the
LLC or to a pulsed output that is active when the LLC is powered for the
purpose of monitoring the LLC power status. If LPS is inactive for more
than 1.2
μ
s and less than 25
μ
s, interface is reset. If LPS is inactive for
greater than 25
μ
s, the PHY will disable the PHY/Link interface to save
power. FW801A continues its repeater function.
Link Request.
LREQ is an output from the LLC that requests the PHY to
perform some service. Bus-keeper circuitry is built into this terminal.
Powerdown.
When asserted high, PD turns off all internal circuitry except
the bias-detect circuits that drive the CNA signal. Internal FW801A logic is
kept in the reset state as long as PD is asserted. PD terminal is provided
for backward compatibility. It is recommended that the FW801A be
allowed to manage its own power consumption using suspend/resume in
conjunction with LPS. C/LKON features are defined in 1394a-2000.
Power for PLL Circuit.
PLLV
DD
supplies power to the PLL circuitry
portion of the device.
Ground for PLL Circuit.
PLLV
SS
is tied to a low-impedance ground
plane.
Current Setting Resistor.
An internal reference voltage is applied to a
resistor connected between R0 and R1 to set the operating current and
the cable driver output current. A low temperature-coefficient resistor
(TCR) with a value of 2.49 k
±
1% should be used to meet the
IEEE
1394-1995 standard requirements for output voltage limits.
Reset (Active-Low).
When /RESET is asserted low (active), the FW801A
is reset. An internal pull-up resistor, which is connected to V
DD
, is provided,
so only an external delay capacitor is required. This input is a standard
logic buffer and can also be driven by an open-drain logic output buffer.
Test Mode Control.
SE is used during the manufacturing test and should
be tied to V
SS
.
Test Mode Control.
SM is used during the manufacturing test and should
be tied to V
SS
.
System Clock.
SYSCLK provides a 49.152 MHz clock signal, which is
synchronized with the data transfers to the LLC.
Analog I/O
Portn, Port Cable Pair A.
TPAn is the port A connection to the twisted-pair
cable. Board traces from each pair of positive and negative differential
signal pins should be kept matched and as short as possible to the external
load resistors and to the cable connector.
Analog I/O
Portn, Port Cable Pair A.
TPAn is the port A connection to the twisted-pair
cable. Board traces from each pair of positive and negative differential
signal pins should be kept matched and as short as possible to the external
load resistors and to the cable connector.
Analog I/O
Portn, Port Cable Pair B.
TPBn is the port B connection to the twisted-pair
cable. Board traces from each pair of positive and negative differential
signal pins should be kept matched and as short as possible to the external
load resistors and to the cable connector.
48
LREQ
I
18
PD
I
41
PLLV
DD
—
42
PLLV
SS
—
37
R0
I
38
R1
45
/RESET
I
23
SE
I
24
SM
I
46
SYSCLK
O
31
TPA0+
30
TPA0
29
TPB0+
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