參數(shù)資料
型號(hào): FW801A
英文描述: Low-Power PHY IEEE 1394A-2000 One-Cable Transceiver/Arbiter Device
中文描述: 低功耗PHY的IEEE 1394A端口,2000年一電纜收發(fā)器/仲裁器裝置
文件頁(yè)數(shù): 4/24頁(yè)
文件大?。?/td> 378K
代理商: FW801A
4
Agere Systems Inc.
FW801A Low-Power PHY
IEEE
1394A-2000
One-Cable Transceiver/Arbiter Device
Data Sheet, Rev. 1
June 2001
Description
(continued)
TPBIAS voltage signal. The midpoint of the pair of
resistors that is directly connected to the twisted-pair B
(TPB) signals is coupled to ground through a parallel
RC network with recommended resistor and capacitor
values of 5 k
and 220 pF, respectively.
The value of the external resistors are specified to
meet the standard specifications when connected in
parallel with the internal receiver circuits.
The driver output current, along with other internal
operating currents, is set by an external resistor. This
resistor is connected between the R0 and R1 signals
and has a value of 2.49 k
±
1%.
The FW801A supports suspend/resume as defined in
the
IEEE
1394a-2000 specification. The suspend
mechanism allows the FW801A port to be put into a
suspended state. In this state, the port is unable to
transmit or receive data packets, however, it remains
capable of detecting connection status changes and
detecting incoming TPBias. When the FW801A port is
suspended, all circuits except the bias voltage
reference generator, and bias detection circuits are
powered down, resulting in significant power savings.
The use of suspend/resume is recommended.
The signal, C/LKON, as an input, indicates whether a
node is a contender for bus manager. When the
C/LKON signal is asserted, it means the node is a con-
tender for bus manager. When the signal is not
asserted, it means that the node is not a contender.
The C bit corresponds to bit 20 in the self-ID packet
(see Table 4-29 of the
IEEE
1394-1995 standard for
additional details).
The power-class bits of the self-ID packet do not have
a default value. These bits can be initialized and read/
written through the LLC using Figure 6-1 (PHY Regis-
ter Map) of the
IEEE
1394a-2000 standard. See Table
8 for the address space of the Pwr_class register.
A powerdown signal (PD) is provided to allow a power-
down mode where most of the PHY circuits are
powered down to conserve energy in battery-powered
applications. The internal logic in FW801A is reset as
long as the powerdown signal is asserted. A cable sta-
tus signal, CNA, provides a high output when none of
the twisted-pair cable ports are receiving incoming
bias voltage. This output is not debounced. The CNA
output can be used to determine when to power the
PHY down or up. In the powerdown mode, all circuitry
is disabled except the CNA circuitry. It should be noted
that when the device is powered down, it does not act
in a repeater mode.
When the power supply of the PHY is removed while
the twisted-pair cables are connected, the PHY trans-
mitter and receiver circuitry has been designed to
present a high impedance to the cable in order to not
load the TPBIAS signal voltage on the other end of the
cable.
For reliable operation, the TPBn signals must be termi-
nated using the normal termination network regardless
of whether a cable is connected to a port or not con-
nected to a port. When the port does not have a cable
connected, internal connect-detect circuitry will keep
the port in a disconnected state.
Note:
All gap counts on all nodes of a 1394 bus must
be identical. This may be accomplished by using
PHY configuration packets (see Section 4.3.4.3
of
IEEE
1394-1995 standard) or by using two
bus resets, which resets the gap counts to the
maximum level (3Fh).
The link power status (LPS) signal works with the
C/LKON signal to manage the LLC power usage of the
node. The LPS signal indicates that the LLC of the
node is powered up or powered down. If LPS is inac-
tive for more than 1.2
μ
s and less than 25
μ
s, PHY/link
interface is reset. If LPS is inactive for greater than
25
μ
s, the PHY will disable the PHY/link interface to
save power. If the PHY then receives a link-on packet,
the C/LKON signal is activated to output a 6.114 MHz
signal, which can be used by the LLC to power itself
up. Once the LLC is powered up, the LPS signal com-
municates this to the PHY and the PHY/link interface
is enabled. C/LKON signal is turned off when LPS is
active or when a bus reset occurs, provided the inter-
rupt that caused C/LKON is not present.
When the PHY/link interface is in the disabled state,
the FW801A will automatically enter a low-power
mode, if all ports are inactive (disconnected, disabled,
or suspended). In this low-power mode, the FW801A
disables its PLL and also disables parts of reference
circuitry depending on the state of the ports (some ref-
erence circuitry must remain active in order to detect
incoming TP bias). The lowest power consumption (the
microlow-power sleep mode) is attained when all ports
are either disconnected or disabled with the ports inter-
rupt enable bit cleared. The FW801A will exit the low-
power mode when the LPS input is asserted high or
when a port event occurs that requires the FW801A to
become active in order to respond to the event or to
notify the LLC of the event (e.g., incoming bias or dis-
connection is detected on a suspended port, a new
connection is detected on a nondisabled port, etc.).
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