參數(shù)資料
型號: FW803
英文描述: PHY IEEE 1394A Three-Cable Transceiver/Arbiter Device
中文描述: PHY的IEEE 1394A端口三線收發(fā)器/仲裁器裝置
文件頁數(shù): 15/24頁
文件大小: 395K
代理商: FW803
Agere Systems Inc.
15
Data Sheet, Rev. 3
June 2001
Three-Cable Transceiver/Arbiter Device
FW803 PHY
IEEE
1394A
Electrical Characteristics
(continued)
Table 5. Device Characteristics
* Device is capable of both differentiated and undifferentiated operation.
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
Supply Current:
One Port Active
All Ports Active
No Ports Active, LPS = 0
PD = 1
High-level Output Voltage
Low-level Output Voltage
High-level Input Voltage
Low-level Input Voltage
Pull-up Current,
/RESET Input
Powerup Reset Time,
/RESET Input
Rising Input Threshold Voltage
/RESET Input
Output Current
V
DD
= 3.3 V
I
DD
I
DD
I
DD
I
DD
V
OH
V
OL
V
IH
V
IL
I
I
1
13
1
51
85
1
0.4
mA
mA
mA
mA
V
V
V
V
μ
A
I
OH
max, V
DD
= min
I
OL
min, V
DD
= max
CMOS inputs
CMOS inputs
V
I
= 0 V
V
DD
– 0.4
0.7V
DD
11
0.2V
DD
32
V
I
= 0 V
2
ms
VI
RST
1.1
1.4
V
SYSCLK
I
OL
/I
OH
@ TTL
I
OL
/I
OH
@ CMOS
I
OL
/I
OH
I
OL
/I
OH
I
I
–16
16
mA
Control, data
–12
12
mA
CNA
C/LKON
V
I
= V
DD
or 0 V
–16
–2
16
2
°
±
1
mA
mA
μ
A
Input Current,
LREQ, LPS, PD, SE, SM,
PC[0:2] Inputs
Off-state Output Current,
CTL[0:1], D[0:7], C/LKON I/Os
Power Status Input Threshold
Voltage, CPS Input
Rising Input Threshold Voltage*,
LREQ, CTLn, Dn
Falling Input Threshold Voltage*,
LREQ, CTLn, Dn
Bus Holding Current,
LREQ, CTLn, Dn
Rising Input Threshold Voltage
LPS
Falling Input Threshold Voltage
LPS
V
O
= V
DD
or 0 V
I
OZ
°
±
5
μ
A
400 k
resistor
V
TH
7.5
8.5
V
V
IT
+
V
DD
/2 + 0.3
V
DD
/2 + 0.8
V
V
IT
V
DD
/2 – 0.8
V
DD
/2 – 0.3
V
V
I
= 1/2(V
DD
)
250
550
μ
A
V
LIH
0.24V
DD
+ 1
V
V
LIL
0.24V
DD
+ 0.2
V
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