參數(shù)資料
型號(hào): FXMA2102L8X
廠商: Fairchild Semiconductor
文件頁數(shù): 15/16頁
文件大?。?/td> 0K
描述: TRANSLATOR/BUFF/REPEAT 8-MLP
標(biāo)準(zhǔn)包裝: 1
邏輯功能: 變換器,雙向,3 態(tài),開路漏極
位數(shù): 2
輸入類型: 電壓
輸出類型: 電壓
通道數(shù): 2
輸出/通道數(shù)目: 1
差分 - 輸入:輸出: 無/無
傳輸延遲(最大): 4ns
電源電壓: 1.65 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
封裝/外殼: 8-UFQFN
供應(yīng)商設(shè)備封裝: 8-MicroPak?
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: FXMA2102L8XDKR
2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FXMA2102
Rev. 1.0.6
8
F
XM
A
2102
Dual
-S
upply
,
2
-Bit
Vol
tage
Tra
nsl
a
to
r/
Buf
fer
/
Repe
a
ter
/
Is
ola
to
rfor
I
2
C
Ap
plic
a
tions
I
2
C-Bus
Isolation
The FXMA2102 supports I
2C-Bus isolation for the
following conditions:
Bus isolation if bus clear
Bus isolation if either V
CC goes to ground
Bus Clear
Because the I
2C specification defines the minimum SCL
frequency of DC, the SCL signal can be held LOW
forever; however, this condition shuts down the I
2C bus.
The I
2C specification refers to this condition as “Bus
Clear”. In Figure 7, if slave #2 holds down SCL forever,
the master and slave #1 are not able to communicate,
because the FXMA2102 passes the SCL stuck-LOW
condition from slave #2 to slave #1 as well as the
master. However, if the OE pin is pulled LOW
(disabled), both ports (A and B) are 3-stated. This
results in the FXMA2102 isolating slave #2 from the
master and slave #1, allowing full communication
between the master and slave #1.
Either VCC to GND
If slave #2 is a camera that is suddenly removed from
the I
2C bus, resulting in V
CCB transitioning from a valid
VCC
(1.65 V
5.5 V)
to
0 V,
the
FXMA2102
automatically forces SCL and SDA on both its A and B
ports into 3-state. Once VCCB has reached 0V, full I
2C
communication between the master and slave #1
remains undisturbed.
Master
FXMA2102
I
2C Buffer
Translator
SCL
SDA
Slave #2
SCL
SDA
VCC = 3.3V
Slave #1
SCL
SDA
VCC = 1.8V
VCCB
VCCA
OE
OE: High Enable
Low Disable
VCCB:
3.3V VCC Domain
VCCA:
1.8V VCC Domain
Figure 7. Bus Isolation
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