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參數(shù)資料
| 型號： | FXMAR2104UMX |
| 廠商： | Fairchild Semiconductor |
| 文件頁數(shù)： | 12/15頁 |
| 文件大?。?/td> | 0K |
| 描述： | TRANSLATOR 4BIT DUAL 12-UMLP |
| 標(biāo)準(zhǔn)包裝： | 5,000 |
| 邏輯功能： | 變換器，雙向，3 態(tài)，開路漏極 |
| 位數(shù)： | 4 |
| 輸入類型： | 電壓 |
| 輸出類型： | 電壓 |
| 數(shù)據(jù)速率： | * |
| 通道數(shù)： | 4 |
| 輸出/通道數(shù)目： | 1 |
| 差分 - 輸入:輸出： | 無/無 |
| 傳輸延遲（最大）： | 4ns |
| 電源電壓： | 1.65 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | * |
| 供應(yīng)商設(shè)備封裝： | * |
| 包裝： | * |
2011 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FXMAR2104 Rev. 1.0.1
6
FXMAR2104
—
Dual-Supply,
4-Bit
Voltage
Translator
/
Isolator
/
for
Open-D
rain
and
Push-Pull
Applications
Application Information
The FXMAR2104 has four bi-directional, open-drain
I/Os and includes a total of eight internal 10K pull-up
resistors (RPUs) on each port of all four data I/O pins. If
a pair of data I/O pins (An/Bn) is not used, these pins
should be left unconnected, eliminating unwanted
current flow through the internal RPUs. External RPUs
can be added to the I/Os to reduce the total RPU value,
depending on the total bus capacitance. The user is free
to lower the total pull-up resistor value to meet the
maximum I
2C edge rate per the I2C specification
(UM10204 rev. 03, June 19, 2007). For example,
according to the I
2C specification, the maximum edge
rate (30% - 70%) during Fast Mode (400kbit/s) is 300ns.
If the bus capacitance is approaching the maximum
400pF, a lower total RPU value helps keep the rise time
below
300ns
(Fast
Mode).
Likewise,
the
I
2C
specification also specifies a minimum SCL high time of
600ns during Fast Mode (400KHz). Lowering the total
RPU also helps increase the SCL high time. If the bus
capacitance
approaches
400pF,
consider
the
FXMA2102, which does not contain internal RPUs.
Then the user can calculate the ideal external RPU
value. Section 7.1 of the I
2C specification provides an
excellent guideline for pull-up resistor sizing.
Theory of Operation
The FXMAR2104 is designed for high-performance level
shifting and buffer / repeating in an I
2C application.
Figure 1 shows that each bi-directional channel contains
two series-Npassgates and two dynamic drivers. This
hybrid architecture is highly beneficial in an I
2C
application where auto-direction is a necessity.
For example, during the following three I
2C protocol
events:
Clock Stretching
Slave’s ACK Bit (9
th bit = 0) following a Master’s
Write Bit (8
th bit = 0)
Clock Synchronization and Multi Master
Arbitration
the bus direction needs to change from master-to-slave
to slave to master without the occurrence of an edge. If
there is an I
2C translator between the master and slave
in these examples, the I
2C translator must change
direction when both A and B ports are LOW. The
Npassgates can accomplish this task very efficiently
because, when both A and B ports are LOW, the
Npassgates act as a low resistive short between the two
(A and B) ports.
Due to I
2C’s open-drain topology, I2C masters and
slaves are not push-pull drivers. Logic LOWs are “pulled
down” (Isink), while logic HIGHs are “l(fā)et go” (3-state). For
example, when the master lets go of SCL (SCL always
comes from the master), the rise time of SCL is largely
determined by the RC time constant, where R = RPU and
C = the bus capacitance. If the FXMAR2104 is attached
to the master [on the A port] and there is a slave on the
B port, the Npassgates act as a low resistive short
between the ports until either of the port’s VCC/2
thresholds are reached. After the RC time constant has
reached the VCC/2 threshold of either port, the port’s
edge detector triggers both dynamic drivers to drive
their
respective
ports
in
the
LOW-to-HIGH
(LH)
direction, accelerating the rising edge. The resulting rise
time resembles the scope shot in Figure 4. Effectively,
two distinct slew rates appear in rise time. The first slew
rate (slower) is the RC time constant of the bus. The
second slew rate (much faster) is the dynamic driver
accelerating the edge.
If both the A and B ports of the translator are HIGH, a
high-impedance path exists between the A and B ports
because both the Npassgates are turned off. If a master
or slave device decides to pull SCL or SDA LOW, that
device’s driver pulls down (Isink) SCL or SDA until the
edge reaches the A or B port VCC/2 threshold. When
either the A or B port threshold is reached, the port’s
edge detector triggers both dynamic drivers to drive
their
respective
ports
in
the
HIGH-to-LOW
(HL)
direction, accelerating the falling edge.
Figure 4. Waveform C: 600pF, Total RPU: 2.2K
Ω
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