Specifications GAL16V8 5 In the Registered mode, macrocells are configured as dedicated registered outputs or as I/O functions. Architecture co" />
參數(shù)資料
型號(hào)： GAL16V8D-10QJN
廠(chǎng)商： Lattice Semiconductor Corporation
文件頁(yè)數(shù)： 24/26頁(yè)
文件大?。?/td> 0K
描述： IC PLD 8MACRO 5.0V 10NS 20PLCC
標(biāo)準(zhǔn)包裝： 46
系列： GAL®16V8
可編程類(lèi)型： EE PLD
最大延遲時(shí)間 tpd(1)： 10.0ns
電壓電源 - 內(nèi)部： 4.75 V ~ 5.25 V
宏單元數(shù)： 8
工作溫度： 0°C ~ 75°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 20-LCC（J 形引線(xiàn)）
供應(yīng)商設(shè)備封裝： 20-PLCC（9x9）
包裝： 管件
Specifications GAL16V8
5
In the Registered mode, macrocells are configured as dedicated
registered outputs or as I/O functions.
Architecture configurations available in this mode are similar to the
common 16R8 and 16RP4 devices with various permutations of
polarity, I/O and register placement.
All registered macrocells share common clock and output enable
control pins. Any macrocell can be configured as registered or I/
O. Up to eight registers or up to eight I/O's are possible in this mode.
Dedicated input or output functions can be implemented as sub-
sets of the I/O function.
Registered outputs have eight product terms per output. I/O's have
seven product terms per output.
The JEDEC fuse numbers, including the User Electronic Signature
(UES) fuses and the Product Term Disable (PTD) fuses, are shown
on the logic diagram on the following page.
Registered Configuration for Registered Mode
- SYN=0.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=0 defines this output configuration.
- Pin 1 controls common CLK for the registered outputs.
- Pin 11 controls common OE for the registered outputs.
- Pin 1 & Pin 11 are permanently configured as CLK &
OE for registered output configuration.
Combinatorial Configuration for Registered Mode
- SYN=0.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=1 defines this output configuration.
- Pin 1 & Pin 11 are permanently configured as CLK &
OE for registered output configuration.
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
DQ
Q
CLK
OE
XOR
Registered Mode
ALL
DEVICES
DISCONTINUED
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GAL16V8D-10QP 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 16 INPUT 8 OUTPUT 5V 1/4 POWER 10ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
GAL16V8D-10QPN 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 16 INPUT 8 OUTPUT 5V 1/4 POWER 10ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
GAL16V8D-15LD/833 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:High Performance E2CMOS PLD Generic Array Logic
GAL16V8D-15LD/883 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Electrically-Erasable PLD
GAL16V8D15LJ 制造商:LATTICE 功能描述:* 制造商:Lattice Semiconductor Corporation 功能描述:
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