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參數(shù)資料
| 型號： | GD14515-68BA |
| 英文描述： | SMPTE |
| 中文描述： | 符合SMPTE |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 129K |
| 代理商： | GD14515-68BA |
Function Details
The major parts of GD14515 are:
u
Clock Multiplying PLL
u
20:1 MUX
u
Scrambler
u
NRZI encoder
u
Two cable driver outputs.
All logic blocks in the design are differen-
tially coupled, i.e. both clocks and signals
are differential. This in conjunction with
the de-coupled power planes in the pack-
age, provide a low jitter content in the se-
rial output data.
The PLL
The Multiplying PLL generates a high-
speed clock of 20 times external clock
source (REFCK), which is preferably
driven differentially for maximum noise
immunity.
The PLL system consists of:
u
a low jitter, wide range VCO running
at 1.2 - 1.5 GHz
u
a Clock Divider,
u
a Set-Reset type Phase-Frequency
Comparator
u
a Charge Pump
The output of the Charge Pump is inte-
grated and filtered outside the chip by
two resistors and a capacitor (
See Figure
3
). The initial values has been deter-
mined to 10 k
and 10 nF, with a resistor
of 330
connected in series with the
charge pump output to decrease loop-
gain. These values can be altered to
achieve the optimal characteristics for
the application.
The 20:1 MUX
The 20:1 MUX can use either forward
clocking or counter clocking:
1. Forward Clocking
The same CMOS-device supplies both
the 20 bit parallel data and the clock for
the REFCK input. Since both clock and
the data come from the same device it is
fairly easy to meet the timing requirement
of the parallel inputs.
Figure 1.
Forward Clocking
2. Counter Clocking
A stand-alone oscillator is used to clock
the REFCK input and then the CKOUT
output is providing the clock for the
CMOS-device supplying the parallel
data. In jitter-sensitive applications this
clocking method provides the better re-
sults as the clock from the CMOS-device
usually has a higher jitter content than a
separate reference oscillator.
However, care must be taken to assure a
low clock-to-data delay in the CMOS-
device to comply to a total round trip de-
lay of less than one cycle of the parallel
clock.
Figure 2.
Counter Clocking
The REFCK input is configured as a dif-
ferential input, but will also operate as
single ended TTL input due to the inter-
nal 1.4 V DC-bias on the inverted input.
Use external de-coupling on inverted in-
put.
To allow the user of GD14515 to com-
pensate for varying external delays in the
parallel data path, two select inputs
(CPH1/0) changes the phase of the inter-
nal clock which loads the parallel data
into the MUX relative to CKOUT (
See
Figure on page 7
).
The NRZI Encoder and
Scrambler
The NRZI encoding and scrambling
polynomium is in accordance with
SMPTE292M:
(X + 1) × (X
9
+ X
4
+ 1)
The Parity Output
A parity output is provided for test pur-
poses. This output is a synchronous
XOR of the parallel input data, but de-
layed two periods of the parallel clock.
Data Sheet Rev. 07
GD14515
Page 2 of 8
REFCK
D
D
CMOS Clock
GD14515
20
20
CKOUT
SOP
SON
U
REFCK
D
D
GD14515
Osc.
20
20
CKOUT
SOP
SON
U
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相關(guān)代理商/技術(shù)參數(shù) |
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