- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375996 > GD14515-68BA SMPTE PDF資料下載
參數(shù)資料
| 型號： | GD14515-68BA |
| 英文描述： | SMPTE |
| 中文描述： | 符合SMPTE |
| 文件頁數(shù)： | 4/8頁 |
| 文件大?。?/td> | 129K |
| 代理商： | GD14515-68BA |
Pin List
Mnemonic:
Pin No.:
Pin Type:
Description:
SOP1
SON1
SOP2
SON2
22, 23
24, 25
27, 28
29, 30
Open Collector
Differential serial data outputs. High speed Open Collector out-
puts to be used with 75
cable or 50
termination for optical
transmitter. Refer to Figure on page 3.
CIP1, CIP2
19, 32
Analog IN
DC-Current control input for SOPx, SONx: 1 mA current into CIPx
generates 25 mA bias for the differential output stage. Maximum
setting is 1.2 mA => 30 mA output stage bias.
DIN0, DIN1
DIN2, DIN3
DIN4, DIN5
DIN6, DIN7
DIN8, DIN9
DIN10, DIN11
DIN12, DIN13
DIN14, DIN15
DIN16, DIN17
DIN18, DIN19
16, 15
13, 12
11, 10
8, 7
6, 5
3, 2
67, 66
64, 63
62, 61
59, 58
TTL IN
Parallel data input. After scrambling and NRZI encoding the data
are shifted to the serial output starting with DIN0 (LSB), followed
by DIN1, DIN2..
CKOUT
57
TTL OUT
Parallel output clock, 74.25 MHz @ 1.485Gbit/s.
REFCK, REFCKN
45, 44
TTL IN
Differential 74.25 MHz @ 1.485Gbit/s reference clock input.
Internal 1.4 V DC-bias on REFCKN can be externally de-coupled
or driven
CPH0, CPH1
54, 53
TTL IN
Phase relation select between CKOUT and the loading of the
parallel data. Data set-up after CKOUT falling edge:
CPH1
CPH0
1
1
T
DEL
= 0
E
0
0
T
DEL
= 90
E
0
1
T
DEL
= 180
E
1
0
T
DEL
= 270
E
SEN
49
TTL IN
Scrambler
“0”
“1”
Enable scrambler
Bypass scrambler and reset registers in scrambler
in maximum eight clock cycles.
NEN
47
TTL IN
NRZI encoder.
“0”
“1”
Enable NRZI
Bypass NRZI and reset NRZI registers
DEN
46
TTL IN
Control of divide divide by 4.
“0”
Disable divide by 4
“1”
Enable divede by 4
NLDET
40
Analog OUT
NLDET is XOR function of REFCK and CKOUT, and outputs are
narrow spikes when PLL is locked. LF filtered output is LO.
VCTL
36
Analog IN
VCO control voltage input.
PFCO
37
Analog OUT
Charge Pump output providing sink or source current for the inte-
grating capacitor in the external loop filter.
TCKEN
39
TTL IN
Bypass VCO input for DC-functional and parametric testing only.
Tie to VEE when not used.
“0”
Enable VCO, disable TCK,TCKN clock input.
“1”
Test mode: Disable VCO, enable TCK,TCKN clock input.
TCK, TCKN
42, 41
Analog IN
Test clock input, see TCKEN. Tie to VEE when not used.
PAR
50
TTL OUT
Parity (synchronuos XOR) of parallel input data delayed 2 cycles.
V3V3
17, 51
PWR
+3.3 V Power for core.
V3V3A
18
PWR
+3.3 V Power for VCO & PFC.
VEE
4, 9, 14, 21, 26, 31,
38, 43, 48, 55, 60,
65
PWR
0V Power.
VCCA
35
PWR
+5 V Power for VCO.
VCC
1, 52, 68
PWR
+5 V Power for TTL I/O.
Data Sheet Rev. 07
GD14515
Page 4 of 8
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GD14516A-68BA | SMPTE |
| GD14526-40BA | SMPTE |
| GD16076A-25SLP | Laser Diode/LED Driver |
| GD16076A-50SLP | Laser Diode/LED Driver |
| GD16131-GLP | ATM Multiplexer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GD14516A-68BA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SMPTE |
| GD14526-40BA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SMPTE |
| GD14NC60K | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:N-channel 14A - 600V -DPAK - D2PAK Short circuit rated PowerMESH TM IGBT |
| GD15 | 制造商:AVX 制造商全稱:AVX Corporation 功能描述:Microwave SLCs ULTRA MAXI Series |
| GD-15 | 功能描述:手工工具 TENSION GAUGES 50-150 Grams RoHS:否 制造商:Molex 產(chǎn)品:Extraction Tools 類型: 描述/功能:Extraction tool |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。