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參數(shù)資料
| 型號： | GD14526-40BA |
| 英文描述： | SMPTE |
| 中文描述： | 符合SMPTE |
| 文件頁數(shù)： | 7/8頁 |
| 文件大小： | 129K |
| 代理商： | GD14526-40BA |
AC Characteristics
Figure 8.
Data Input Set-up and Hold Time vs. CKOUT for CPH1/0 = 11,00,01,10
T
CASE
= 0
°
C to 70
°
C, V
CC
= 5.0 V, V
3V3
= 3.3 V
Symbol:
Characteristic:
Conditions:
MIN.:
TYP.:
MAX.:
UNIT:
J
Tim
Timing Jitter
10 Hz < F < 150 MHz (Note1)
1.0
UI
P-P
J
Alg
Alignment Jitter
100 kHz < F < 150 MHz (Note1)
0.2
UI
P-P
J
Trf
Jitter Transfer
F < Loop bandwidth (Note 2)
0.1
dB
T
TLH SON/SOP
SOP/SON Rise Time
1 m cable, 75
load (Note 4)
1 m cable, 75
load (Note 4)
270
ps
T
THL SON/SOP
SOP/SON Fall Time
270
ps
F
VCO
VCO Frequency Range
1200
1500
MHz
C
DUTY
REFCK
REFCK Clock Duty Cycle
V
Thresh.
= 1.4 V
40
60
%
C
DUTY
CKOUT
Output Clock Duty Cycle
Note 3
45
55
%
T
TLH
Clock
CKOUT Rise Time
20-80% (Note 3)
2000
ps
T
THL
Clock
CKOUT Fall Time
80-20% (Note 3)
2000
ps
T
SA Data
DIN Set-up before CKOUT
CPH1/0 = 11 (See Figure)
0
ps
T
HA Data
DIN Hold after CKOUT
CPH1/0 = 11 (See Figure)
1200
ps
N
Serial-Parallel
no. of bits stored in pipe-lines
25
55
bits
Note 1:
Note 2:
1 UI (serial) = 673 ps. Measured according to RP184: Measurement of Jitter in Bit-Serial Digital Interfaces.
Transfer Jitter = 20log J
SOP
/J
REFCK
within frequency range. F
C
is loop filter dependant, see figure. The choice of F
C
is a
trade off between Jitter Transfer reduction and VCO Phase Noise Suppression. Through careful filter design, loop
peaking may be controlled which is the major contribute to Jitter Transfer.
Threshold voltage = 1.4 V. Load = 500
|| 20 pF to 1.4 V.
Measured as 20/80%. Applies for both cable drivers ( SOP1/SON1 and SOP2/SON2).
Note 3:
Note 4:
Reference Standards
SMPTE 292M (May 7, 1996): Bit-Serial Digital Interface for HDTV
SMPTE RP184 (December 1, 1996): Measurement of Jitter in Bit-serial Digital Interfaces.
Data Sheet Rev. 07
GD14515
Page 7 of 8
T
SB
T
SA
DIN0..19
CKOUT
T
SC
T
SD
T
HB
T
HA
T
HC
T
HD
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