參數(shù)資料
型號(hào)： GF9330
英文描述： GF9330 - High Performance HDTV/SDTV Deinterlacer
中文描述： GF9330 -高性能高清/標(biāo)清去隔行掃描
文件頁(yè)數(shù)： 10/34頁(yè)
文件大?。?/td> 550K
代理商： GF9330
GENNUM CORPORATION
18283 - 3
10
G
DETAILED DEVICE DESCRIPTION
1. SUPPORTED INPUT VIDEO FORMATS
The GF9330 supports multiple input data formats with
multiplexed or separate Y/C channels. Data is supplied to
the GF9330 through the Y_IN[9:0] and the C_IN[9:0]
busses. Table 1 outlines the data formats that are
supported according to the setting of the control register
bits STD[4:0]
Note: For all progressive video standards the GF9330 must
be manually set to bypass mode (MODE[2:0] = 111). See
Section 5 for details.
TABLE 1: Encoding of STD[4:0] for Selecting Input Data Format
STD
STD[4:0]
DESCRIPTION
0
00000
525i (30/1.001) component SMPTE 125M. Multiplexed Y Cb Cr data applied to Y_IN. C_IN is set low.
Note: Input clock is 27MHz.
1
00001
RESERVED.
2
00010
525i (30/1.001) component 16x9 SMPTE 267M. Multiplexed Y Cb Cr data applied to Y_IN. C_IN is set low.
Note: Input clock is 36MHz.
3
00011
RESERVED
4
00100
625i (25Hz) component EBU tech. 3267E. Multiplexed Y Cb Cr data applied to Y_IN. C_IN is set low.
Note: Input clock is 27MHz.
5
00101
RESERVED
6
00110
625i (25Hz) component 16x9 ITU-R BT.601-5 Part B. Multiplexed Y Cb Cr data applied to Y_IN. C_IN is set
low. Note: Input clock is 36MHz.
7
00111
RESERVED
8
01000
525p (60/1.001Hz) SMPTE 293M. Y Cb Cr data stream applied to Y_IN. C_IN is set low.
Note: Input clock is 54MHz.
9
01001
RESERVED
10
01010
RESERVED
11
01011
RESERVED
12
01100
625p (50Hz) ITU-R BT.1358. Y Cb Cr data stream applied to Y_IN. C_IN is set low.
Note: Input clock is 54MHz.
13
01101
625p (50Hz) 16 x 9 with 18MHz sampling. Y Cb Cr data stream applied to Y_IN. C_IN is set low.
Note: Input clock is 72MHz.
14
01110
Generic SD input data format with 4:1:1 sampling. Y Cb Cr data is applied to both Y_IN and C_IN. Externally
supplied F_IN, V_IN and H_IN signals are used to synchronize the input data stream.
Note: Input clock is 27MHz.
15
01111
Generic SD nput data format with 4:2:2 sampling and single multiplexed Y Cb Cr nput format.
Y Cb Cr data applied to Y_IN. C_IN is set low. Externally supplied F_IN, V_IN and H_IN signals are used to
synchronize the input data stream. Note: Input clock is 27 or 36MHz.
16
10000
720p (60 & 60/1.001Hz) SMPTE 296M-2001. Y Data applied to Y_IN. Cb Cr data applied to C_IN. Note: Input
clock is 74.25 MHz or 74.25/1.001MHz.
17
10001
720p (30 & 30/1.001Hz) SMPTE 296M-2001. Y Data applied to Y_IN. Cb Cr data applied to C_IN.
Note: Input clock is 74.2 or 74.2/1.001MHz.
18
10010
1080p (30 & 30/1.001Hz) SMPTE 274M. Y data applied to Y_IN. Cb Cr data applied to C_IN.
Note: Input clock is 74.25MHz or 74.25/1.001MHz.
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