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參數(shù)資料
| 型號(hào)： | GL800 |
| 英文描述： | GL800 USB 2.0 UTMI Compliant Transceiver |
| 中文描述： | GL800采用UTMI兼容的USB 2.0收發(fā)器 |
| 文件頁(yè)數(shù)： | 11/24頁(yè) |
| 文件大?。?/td> | 832K |
| 代理商： | GL800 |
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GL800USB - USB2.0 UTMI COMPLIANT TRANSCEIVER
Pin #
Name
I/O
Pull
Up/Down
Description
20
RXACTV
O
Receive Active
, active high. Indicates that the
receive state machine has detected SYNC and is
active. RXACTV is negated after a Bit Stuff Error
or an EOP is detected.
In HS mode, RXACTV must be negated no less
than 3 and no more than 8 CLKs after an Idle
state is detected on the USB. And RXACTV must
be negated for at least 1 CLK between
consecutive received packets.
In FS/FS only modes, RXACTV must be negated
no more than 2 CLKs after a FS Idle state is
detected on the USB. And RXACTV must be
negated for at least 4 CLKs between consecutive
received packets.
Receive Error
, active high.
0: Indicates no error.
1: Indicates that a receive error has been detected.
This output is clocked with the same timing as the
Data lines and can occur at anytime during a
transfer. If asserted, it will force the negation of
RXVLD on the next rising edge of CLKOUT.
Receive Data Valid
, active high. Indicates that
the Data bus has valid data. The Rx Register is
full and ready to be unloaded. The SIE is
expected to latch the Data bus on the clock edge.
Clock.
This 30MHz clock output is used for
clocking receive and transmit HS/FS 16-bit
parallel data.
Transmit Valid
, active high. Indicates that the
Data bus is valid. The assertion of Transmit Valid
initiates SYNC on the USB. The negation of
Transmit Valid initiates EOP on the USB.
In HS mode, the SYNC pattern must be asserted
on the USB between 8 and 16 bit times after the
assertion of TXVLD is detected by the Transmit
State Machine.
In FS/ FS only Modes, the SYNC pattern must be
asserted on the USB no less than 1 CLK and no
more than 5 CLKs after the assertion of TXVLD is
detected by the Transmit State Machine.
Transmit/Receive Valid High
, active high.
21
RXERR
O
22
RXVLD
O
23
CLKOUT
O
24
TXVLD
I
25
VALIDH
B
2000-2001 Genesys Logic Inc.—All rights reserved.
Page 11 of 11
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相關(guān)代理商/技術(shù)參數(shù) |
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| GL800HT25 | 制造商:GENESYS 制造商全稱:GENESYS 功能描述:USB 2.0 UTMI Compliant Transceiver IP Core |
| GL80-RT/32/40A/98A | 制造商:PEPPERL+FUCHS 功能描述:Sensor, Photoelectric, Slot |
| GL811 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:GL811 USB 2.0 to ATA/ATAPI Controller |
| GL811E | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:USB 2.0 to ATA / ATAPI Bridge Controller |
| GL811E-04G | 制造商:GENESYS-LOGIC 功能描述: |
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