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參數(shù)資料
| 型號： | GL800 |
| 英文描述： | GL800 USB 2.0 UTMI Compliant Transceiver |
| 中文描述： | GL800采用UTMI兼容的USB 2.0收發(fā)器 |
| 文件頁數(shù)： | 16/24頁 |
| 文件大小： | 832K |
| 代理商： | GL800 |
GL800USB - USB2.0 UTMI COMPLIANT TRANSCEIVER
Reset
!RXACTV
!RXVLD
RX Wait
Trip SYNC
RXACTV
Rx Data
RXVLD
RX Data Wait
!RXVLD
Strip EOP
!RXACTV
!RXVLD
HRST#
!HRST#
SYNC Detected
Data
!Data
!SYNC
Idle
state
!Data
Data
Abort 1
!RXACTV
!RXVLD
!RXERR
Terminate
!RXACTV
Abort 2
!RXVLD
!RXERR
!Idle
state
Error
RXERR
EOP
Detected
Receive
Error
Data
SYNC
z
RXACTV and RXVLD are sampled on the rising edge of CLKOUT.
z
In the RX Wait state the receiver is always looking for SYNC.
z
The Macrocell asserts RXACTV when SYNC is detected (Strip SYNC state).
z
The Macrocell negates RXACTV when an EOP is detected (Strip EOP state).
z
When RXACTV is asserted, RXVLD will be asserted if the RX Holding Register is
full.
z
RXVLD will be negated if the RX Holding Register was not loaded during the
previous byte time. This will occur if 8 stuffed bits have been accumulated.
z
The SIE must be ready to consume a data byte if RXACTV and RXVLD are asserted
(RX Data state).
z
In FS mode, if a bit stuff error is detected then the Receive State Machine will negate
RXACTV and RXVLD, and return to the RXWait state.
6.2.2 Receive Timing for Data Packet (with CRC-16)
2000-2001 Genesys Logic Inc.—All rights reserved.
Page 16 of 16
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GL800HT25 | 制造商:GENESYS 制造商全稱:GENESYS 功能描述:USB 2.0 UTMI Compliant Transceiver IP Core |
| GL80-RT/32/40A/98A | 制造商:PEPPERL+FUCHS 功能描述:Sensor, Photoelectric, Slot |
| GL811 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:GL811 USB 2.0 to ATA/ATAPI Controller |
| GL811E | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:USB 2.0 to ATA / ATAPI Bridge Controller |
| GL811E-04G | 制造商:GENESYS-LOGIC 功能描述: |
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