參數(shù)資料
型號: GL811
英文描述: GL811 USB 2.0 to ATA/ATAPI Controller
中文描述: GL811 USB 2.0至ATA / ATAPI控制器
文件頁數(shù): 16/36頁
文件大?。?/td> 291K
代理商: GL811
GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller
2000-2002 Genesys Logic Inc.—All rights reserved.
Page 15
6.4.1 Register transfers
Notes:
1. Device address consists of signals CS0_, CS1_ and DA(2:0).
2. Data consists of IODD(7:0).
3. The negation of IORDY by the device is used to extend the register transfer cycle. The
determination of whether the cycle is to be extended is made by the host after t
A
from the
assertion of DIOR_ or DIOW_. The assertion and negation of IORDY are described as
following:
t
0
t
1
t
2
t
9
t
2i
t
3
t
4
t
5
t
6
t
6z
t
A
t
C
t
RD
t
C
t
B
ADDR valid
(Note1)
DIOR_/DIOW_
WRITE IODD(7:0)
(Note2)
Read IODD(7:0)
(Note2)
IORDY (Note3.1)
IORDY (Note3.2)
IORDY (Note3.3)
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