參數(shù)資料
型號: GL811
英文描述: GL811 USB 2.0 to ATA/ATAPI Controller
中文描述: GL811 USB 2.0至ATA / ATAPI控制器
文件頁數(shù): 17/36頁
文件大小: 291K
代理商: GL811
GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller
2000-2002 Genesys Logic Inc.—All rights reserved.
Page 16
3.1 Device never negates IORDY, devices keeps IORDY released: no wait is generated.
3.2 Device negates IORDY before t
A
, but causes IORDY to be asserted before t
A
. IORDY is
released prior to negation and may be asserted for no more than 5 ns before release: no
wait generated.
3.3 Device negates IORDY before t
A
, IORDY is released prior to negation and may be
asserted for no more than 5 ns before release: wait generated. The cycle completes after
IORDY is released. For cycles where a wait is generated and DIOR_ is asserted, the
device shall read data on IODD(0:7) for t
RD
before asserting IORDY.
4. DMACK_ shall remain negated during a register transfer.
Register transfer timing parameters
Timing (ns)
t
0
Cycle time
2000
t
1
Address valid to DIOR_/ DIOW_ setup
1000
t
2
DIOR_/ DIOW_ pulse width 8-bit
300
t
2i
DIOR_/ DIOW_ recovery time
900
t
3
DIOW_ data setup
80
t
4
DIOW_ data hold
40
t
5
DIOR_ data setup
-
t
6
DIOR_ data hold
-
t
6Z
DIOR_ data tristate
-
t
9
DIOR_/ DIOW_ to address valid hold
900
t
RD
Read Data Valid to IORDY active
(if IORDY initially low after t
A
)
t
A
IORDY Setup time
-
t
B
IORDY Pulse Width
-
t
C
IORDY assertion to release (max)
-
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