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參數(shù)資料
| 型號： | GP2021 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | GPS 12 channel Correlator(用于全球定位系統(tǒng)（GPS）接收器的12通道的C/A代碼基帶相關(guān)器) |
| 中文描述： | 全球定位系統(tǒng)12通道相關(guān)器（用于全球定位系統(tǒng)（GPS）的接收器的12通道的C / A電代碼基帶相關(guān)器） |
| 文件頁數(shù)： | 56/62頁 |
| 文件大?。?/td> | 371K |
| 代理商： | GP2021 |
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6
GP2021
Pin No
Signal Name
Type
Description ARM System Mode
Description Standard Interface
Mode
31
ABORT/ MICRO_CLK
O
Abort output to the microprocessor.
20MHz Clock output. Provides a
Generates a valid ARM Data Abort
20MHz clock with a 1:1
sequence, triggered by a rising edge
mark-to-space ratio
at MULTI_FN_IO if this function is
enabled.
32
DISCIO
I/O
Multi–purpose discrete input / output. After a GP2021 reset it is
configured as an input.
33
A22 / READ
I
Address input from the microprocessor.
Read input from the
A<22:20> are decoded to select the
microprocessor. In Intel mode
address space partitioning.
it is the active Low read strobe.
In Motorola mode it is the Read
(High)/Write (Low) select line.
36
A21 / NCS
I
Address input from the microprocessor.
GP2021 Chip Select input
A<22:20> are decoded to select the
(Active Low).
address space partitioning.
37
A20 / WREN
I
Address input from the microprocessor
Write–Read Strobe input from
A<22:20> are decoded to select the
the microprocessor. In Intel
address space partitioning.
mode it is the active Low write
strobe. In Motorola mode it is
the active High Write-Read
strobe.
38 – 45
A<9:2>
I
Address Inputs <9:2> from the microprocessor. These allow register
selection.
46
A1 / ALE_IP
I
Address input 1 from the
Address Latch Enable input
microprocessor. A<1:0> are decoded
from microprocessor (Active
to provide individual byte write
High)
selection via NW<3:0>.
47
A0 / NRESET_IP
I
Address input 0 from the
Reset input (Active Low).
microprocessor. A<1:0> are decoded
to provide individual byte write
selection via NW<3:0>.
48– 54,
D<0:15>
I/O
57–65
66
PLL_LOCK
I
PLL Lock Indicator input from RF section. When High this signa
indicates that the PLL within the RF section is in lock and the master
clock inputs have stabilised.
68
DISCOP
O
Multi–purpose discrete output.
70
CLK_T
I
Master clock input (40MHz).
71
CLK_I
I
Inverted Master clock input.
73
SAMPCLK
O
Sample Clock output to the front end. Provides a 5.714MHz clock with a
4:3 mark–to–space ratio.
75
NBRAM / DISCIP4
I
Battery Backed RAM select input.
Multi–purpose discrete input.
Defines the state of the NRAM output in
Power Down mode.
76
SIGN0
I
SIGN0 input from the RF section.
77
MAG0
I
MAG0 input from the RF section.
78
SIGN1
I
SIGN1 input from a second, optional, RF section.
79
MAG1
I
MAG1 input from a second, optional, RF section.
80
DISCIP1
I
Multi–purpose discrete input.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GP2021 | GPS 12 channel Correlator Advance Information |
| GRM40Y5V105Z16 | Circular Connector; MIL SPEC:MIL-C-26482, Series I, Solder; Body Material:Aluminum; Series:PT06; No. of Contacts:21; Connector Shell Size:22; Connecting Termination:Solder; Circular Shell Style:Straight Plug; Body Style:Straight |
| GRM42-6X5R475K10 | 50/100M SOT-23 CMOS RF LDO REGULATORS |
| GT- 32090 | Highly Integrated Single-Chip System Controller(高集成單片系統(tǒng)控制器) |
| GT-48001A | Switched Ethernet Controller For 10BaseX(10BaseX交換式快速以太網(wǎng)控制器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GP2021IGGQ1R | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Correlator |
| GP202K | 制造商:GTM 制造商全稱:GTM 功能描述:SURFACE MOUNT,SWITCHING DIODE |
| GP2030S | 制造商:GTM 制造商全稱:GTM 功能描述:N AND P-CHANNEL ENHANCEMENT MODE POWER MOSFET |
| GP2-031X250-50 | 制造商:GROOV-PIN 功能描述: |
| GP204 | 制造商:DEC 制造商全稱:DEC 功能描述:2 AMP SOFT GLASS PASSIVATED DIODES |
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