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參數(shù)資料
| 型號： | GS1545-CQR |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | HDTV Serial Digital Equalizing Receiver |
| 中文描述： | 串行數(shù)字高清晰度電視接收機均等 |
| 文件頁數(shù)： | 15/19頁 |
| 文件大?。?/td> | 198K |
| 代理商： | GS1545-CQR |
GENNUM CORPORATION
522 - 28 - 00
15
G
Fig. 23 PLL Circuit Principles
If the signal is not locked, the data transition phase could
be anywhere with respect to the internal clock or the
quadrature clock. In this case, the normalized filtered
sample of the quadrature clock will be 0.5. When VCO is
locked to the incoming data, data will only sample the
quadrature clock when it is logic high. The normalized
filtered sample quadrature clock will be 1.0. We chose a
threshold of 0.66 to generate the phase lock signal.
Because the threshold is lower than 1, it allows jitter to be
greater than 0.5UI before the phase lock circuit reads it as
“
not phase locked
”
.
INPUT JITTER INDICATOR (IJI)
This signal indicates the amount of excessive jitter (beyond
the quadrature clock window 0.5UI), which occurs beyond
the quadrature clock window (see Figure 23) All the input
data transitions occurring outside the quadrature clock
window, will be captured and filtered by the low pass filter
as mentioned in the Phase Lock section. The running time
average of the ratio of the transitions inside the quadrature
clock and outside the quadrature is available at the
PLCAP/PLCAP pins. A signal, IJI, which is the buffered
signal available at the PLCAP is provided so that loading
does not effect the filter circuit. The signal at IJI is
referenced with the power supply such that the factor
V
IJI
/V
CC
is a constant over process and power supply for a
given input jitter modulation. The IJI signal has 10k
output
impedance. Figure 24 shows the relationship of the IJI
signal with respect to the sine wave modulated input jitter.
Fig. 24 Input Jitter Indicator (Typical at T
A
= 25
°
C)
JITTER DEMODULATION (DM)
The differential jitter demodulation (DM) signal is available
at the DM and DM pins. This signal is the phase correction
signal of the PLL loop, which is amplified and buffered. If
the input jitter is modulated, the PLL tracks the jitter if it is
within loop bandwidth. To track the input jitter, the VCO has
to be adjusted by the phase detector via the charge pump.
Thus, the signal which controls the VCO contains the
information of the input jitter modulation. The jitter
demodulation signal is only valid if the input jitter is less
than 0.5UIp-p. The DM/DM signals have 10k
output
impedance, which could be low pass filtered with
appropriate capacitors to eliminate high frequency noise.
DFT_V
EE
should be connected to GND to activate DM/DM
signals.
The DM signals can be used as diagnostic tools. Assume
there is an HDTV SDI source, which contains excessive
noise during the horizontal blanking because of the
transient current flowing in the power supply. In order to
discover the source of the noise, one could probe around
IN-PHASE CLOCK
INPUT DATA
WITH JITTER
0.5UI
RE-TIMING
EDGE
PHASE ALIGNMENT
EDGE
QUADERATURE
CLOCK
PLCAP SIGNAL
PLCAP SIGNAL
0.25UI
P-P SINE WAVE JITTER IN UI
IJI VOLTAGE
0.00
4.75
0.15
4.75
0.30
4.75
0.39
4.70
0.45
4.60
0.48
4.50
0.52
4.40
0.55
4.30
0.58
4.20
0.60
4.10
0.63
3.95
I
INPUT JITTER (UI)
0.00 0.20 0.40 0.60 0.80
5.0
4.8
4.6
4.4
4.2
4.0
3.8
3.6
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