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參數資料
| 型號： | GS71108AGU-10I |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | SRAM |
| 英文描述： | 128K X 8 STANDARD SRAM, 10 ns, PBGA48 |
| 封裝： | 6 X 8 MM, ROHS COMPLIANT, 0.75 MM PITCH, FBGA-48 |
| 文件頁數： | 9/11頁 |
| 文件大?。?/td> | 419K |
| 代理商： | GS71108AGU-10I |
Write Cycle
Parameter
Symbol
-7
-8
-10
-12
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Write cycle time
tWC
7
—
8
—
10
—
12
—
ns
Address valid to end of write
tAW
5
—
5.5
—
7
—
8
—
ns
Chip enable to end of write
tCW
5
—
5.5
—
7
—
8
—
ns
Data set up time
tDW
3
—
4
—
5
—
6
—
ns
Data hold time
tDH
0
—
0
—
0
—
0
—
ns
Write pulse width
tWP
5
—
5.5
—
7
—
8
—
ns
Address set up time
tAS
0
—
0
—
0
—
0
—
ns
Write recovery time (WE)
tWR
0
—
0
—
0
—
0
—
ns
Write recovery time (CE)
tWR1
0
—
0
—
0
—
0
—
ns
Output Low Z from end of write
tWLZ*
3
—
3
—
3
—
3
—
ns
Write to output in High Z
tWHZ*
—
3
—
3.5
—
4
—
5
ns
GS71108AU
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.10a 3/2011
7/11
2001, GSI Technology
* These parameters are sampled and are not 100% tested
tWC
Address
CE
WE
Data In
OE
Data Out
tAW
tCW
tAS
tWP
tWR
tDW
tDH
tWLZ
tWHZ
DATA VALID
HIGH IMPEDANCE
Write Cycle 1: WE control
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| GS71108AGU-12 | 制造商:GSI Technology 功能描述:SRAM ASYNC SGL 3.3V 1MBIT 128KX8 12NS 48FBGA - Trays |
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| GS71108AGU-7 | 制造商:GSI Technology 功能描述:SRAM ASYNC SGL 3.3V 1MBIT 128KX8 7NS 48FBGA - Trays |
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| GS71108AGU-8 | 制造商:GSI Technology 功能描述:SRAM ASYNC SGL 3.3V 1MBIT 128KX8 8NS 48FBGA - Trays |
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