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參數(shù)資料
| 型號： | GS8182S18BD-300IT |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | SRAM |
| 英文描述： | 1M X 18 DDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1 MM PITCH, FPBGA-165 |
| 文件頁數(shù)： | 34/37頁 |
| 文件大?。?/td> | 564K |
| 代理商： | GS8182S18BD-300IT |
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Pin Description Table
Symbol
Description
Type
Comments
SA
Synchronous Address Inputs
Input
—
R/W
Read/Write Contol Pin
Input
Write Active Low; Read Active High
NW0–NW1
Synchronous Nybble Writes
Input
Active Low
x08 Only
BW
Synchronous Byte Writes
Input
Active Low
x09 Only
BW0–BW3
Synchronous Byte Writes
Input
Active Low
x18/x36 Only
K
Input Clock
Input
Active High
C
Output Clock
Input
Active High
TMS
Test Mode Select
Input
—
TDI
Test Data Input
Input
—
TCK
Test Clock Input
Input
—
TDO
Test Data Output
Output
—
VREF
HSTL Input Reference Voltage
Input
—
ZQ
Output Impedance Matching Input
Input
—
K
Input Clock
Input
Active Low
C
Output Clock
Output
Active Low
DOFF
DLL Disable
—
Active Low
LD
Synchronous Load Pin
—
Active Low
CQ
Output Echo Clock
Output
Active Low
CQ
Output Echo Clock
Output
Active High
Dn
Synchronous Data Inputs
Input
—
Qn
Synchronous Data Outputs
Output
—
VDD
Power Supply
Supply
1.8 V Nominal
VDDQ
Isolated Output Buffer Supply
Supply
1.8 or 1.5 V Nominal
VSS
Power Supply: Ground
Supply
—
NC
No Connect
—
Notes:
1. C, C, K, or K cannot be set to VREF voltage.
2. When ZQ pin is directly connected to VDD, output impedance is set to minimum value and it cannot be connected to ground or left
unconnected.
3. NC = Not Connected to die or any other pin.
GS8182S08/09/18/36BD-400/375/333/300/250/200/167
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03b 6/2010
6/37
2007, GSI Technology
Background
Separate I/O SRAMs, like SigmaQuad SRAMs, are attractive in applications where alternating reads and writes are needed. On the
other hand, Common I/O SRAMs like the SigmaCIO family are popular in applications where bursts of read or write traffic are
needed. The SigmaSIO SRAM is a hybrid of these two devices. Like the SigmaQuad family devices, the SigmaSIO features a
separate I/O data path, offering the user independent Data In and Data Out pins. However, the SigmaSIO devices offer a control
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PDF描述 |
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| GS8182S18BD-250I | 1M X 18 DDR SRAM, 0.45 ns, PBGA165 |
| GS8182S18BD-300I | 1M X 18 DDR SRAM, 0.45 ns, PBGA165 |
| GS8182T08GBD-167IT | 2M X 8 DDR SRAM, 0.5 ns, PBGA165 |
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相關(guān)代理商/技術(shù)參數(shù) |
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| GS8182S18D-250 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 18MBIT 1MX18 0.45NS 165FBGA - Trays |
| GS8182S18D-250I | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 18MBIT 1MX18 0.45NS 165FPBGA - Trays |
| GS8182S36BD-167 | 制造商:GSI Technology 功能描述:512K X 36 (18 MEG) BURST OF 2 - Trays |
| GS8182S36BD-167I | 制造商:GSI Technology 功能描述:512K X 36 (18 MEG) BURST OF 2 - Trays |
| GS8182S36BD-200 | 制造商:GSI Technology 功能描述:512K X 36 (18 MEG) BURST OF 2 - Trays |
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