參數(shù)資料
型號(hào)： GS8182T08GBD-167IT
廠商： GSI TECHNOLOGY
元件分類： SRAM
英文描述： 2M X 8 DDR SRAM, 0.5 ns, PBGA165
封裝： 13 X 15 MM, ROHS COMPLIANT, FPBGA-165
文件頁(yè)數(shù)： 1/37頁(yè)
文件大?。?/td> 340K
代理商： GS8182T08GBD-167IT
Preliminary
GS8182T08/09/18/36BD-333/300/267/250/200/167
18Mb SigmaCIO DDR-II
Burst of 2 SRAM
333 MHz–167 MHz
1.8 V VDD
1.8 V and 1.5 V I/O
165-Bump BGA
Commercial Temp
Industrial Temp
Rev: 1.00a 6/2007
1/37
2007, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Features
Simultaneous Read and Write SigmaCIO Interface
Common I/O bus
JEDEC-standard pinout and package
Double Data Rate interface
Byte Write (x36 and x18) and Nybble Write (x8) function
Burst of 2 Read and Write
1.8 V +100/–100 mV core power supply
1.5 V or 1.8 V HSTL Interface
Pipelined read operation with self-timed Late Write
Fully coherent read and write pipelines
ZQ pin for programmable output drive strength
IEEE 1149.1 JTAG-compliant Boundary Scan
Pin-compatible with present 9Mb, 36Mb, and 72Mb and
future 144Mb devices
165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
RoHS-compliant 165-bump BGA package available
SigmaCIO Family Overview
The GS8182T08/09/18/36BD are built in compliance with the
SigmaCIO DDR-II SRAM pinout standard for Common I/O
synchronous SRAMs. They are 16,777,216-bit (18Mb)
SRAMs. The GS8182T08/09/18/36BD SigmaCIO SRAMs are
just one element in a family of low power, low voltage HSTL
I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
Clocking and Addressing Schemes
The GS8182T08/09/18/36BD SigmaCIO DDR-II SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer. The device also allows the user to manipulate the
output register clock inputs quasi independently with the C and
C clock inputs. C and C are also independent single-ended
clock inputs, not differential inputs. If the C clocks are tied
high, the K clocks are routed internally to fire the output
registers instead.
Common I/O x36 and x18 SigmaCIO DDR-II B2 RAMs
always transfer data in two packets. When a new address is
loaded, A0 presets an internal 1 bit address counter. The
counter increments by 1 (toggles) for each beat of a burst of
two data transfer.
Common I/O x8 SigmaCIO DDR-II B2 RAMs always transfer
data in two packets. When a new address is loaded, the LSB
is internally set to 0 for the first read or write transfer, and
incremented by 1 for the next transfer. Because the LSB is
tied off internally, the address field of a x8 SigmaCIO DDR-II
B4 RAM is always one address pin less than the advertised
index depth (e.g., the 2M x 9 has a 1M addressable index).
Parameter Synopsis
-333
-300
-267
-250
-200
-167
tKHKH
3.0 ns
3.3 ns
3.75 ns
4.0 ns
5.0 ns
6.0 ns
tKHQV
0.45 ns
0.5 ns
165-Bump, 13 mm x 15 mm BGA
1 mm Bump Pitch, 11 x 15 Bump Array
Bottom View
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS8182T09BD-375 制造商:GSI Technology 功能描述:SRAM SYNC SGL 1.8V 18MBIT 2M X 9 0.45NS 165FPBGA - Trays
GS8182T09BD-400 制造商:GSI Technology 功能描述:SRAM SYNC SGL 1.8V 18MBIT 2M X 9 0.45NS 165FPBGA - Trays
GS8182T18BD-167 制造商:GSI Technology 功能描述:SRAM SYNC SGL 1.8V 18MBIT 1MX18 0.5NS 165FPBGA - Trays
GS8182T18BGD-250I 制造商:GSI Technology 功能描述:SRAM SYNC SGL 1.8V 18MBIT 1MX18 0.45NS 165FPBGA - Trays
GS8182T19BD-435 制造商:GSI Technology 功能描述:SRAM SYNC SGL 1.8V 18MBIT 1MX18 0.45NS 165FPBGA - Trays
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