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參數(shù)資料
| 型號(hào)： | GS820V32T5I |
| 英文描述： | x32 Fast Synchronous SRAM |
| 中文描述： | X32號(hào)，快速同步SRAM |
| 文件頁數(shù)： | 3/23頁 |
| 文件大?。?/td> | 649K |
| 代理商： | GS820V32T5I |
Rev: 1.08 2/2001
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
3/23
2000, Giga Semiconductor, Inc.
GS82032AT/Q-200/180/166/133/100
TQFP Pin Description
Pin Location
Symbol
A
0
, A
1
Type
I
Description
37, 36
Address field LSBs and Address Counter preset Inputs
35, 34, 33, 32, 100, 99, 82, 81, 44, 45,
46, 47, 48, 49
52, 53, 56, 57, 58, 59, 62, 63
68, 69, 72, 73, 74, 75, 78, 79
2, 3, 6, 7, 8, 9, 12, 13
18, 19, 22, 23, 24, 25, 28, 29
16, 38, 39, 42, 43, 66, 50, 51, 80, 1, 30
87
93, 94
95, 96
89
88
98, 92
97
86
83
84, 85
64
14
31
A
2
–A
15
I
Address Inputs
DQ
A1
–DQ
A8
DQ
B1
–DQ
B8
DQ
C1
–DQ
C8
DQ
D1
–DQ
D8
NC
BW
B
A
, B
B
B
C
, B
D
CK
GW
E
1
, E
3
E
2
G
ADV
ADSP, ADSC
ZZ
FT
LBO
V
DD
V
SS
V
DDQ
I/O
Data Input and Output pins
No Connect
I
I
I
I
I
I
I
I
I
I
I
I
I
Byte Write—Writes all enabled bytes; active low
Byte Write Enable for DQ
A
, DQ
B
Data I/Os; active low
Byte Write Enable for DQ
C
, DQ
D
Data I/Os; active low
Clock Input Signal; active high
Global Write Enable—Writes all bytes; active low
Chip Enable; active low
Chip Enable; active high
Output Enable; active low
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
Sleep Mode control; active high
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
15, 41, 65, 91
I
Core power supply
5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90
I
I/O and Core Ground
4, 11, 20, 27, 54, 61, 70, 77
I
Output driver power supply
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