參數(shù)資料
型號(hào)： GS8320V32GT-166IT
廠商： GSI TECHNOLOGY
元件分類(lèi)： SRAM
英文描述： 1M X 32 CACHE SRAM, 8 ns, PQFP100
封裝： LEAD FREE, TQFP-100
文件頁(yè)數(shù)： 1/24頁(yè)
文件大?。?/td> 655K
代理商： GS8320V32GT-166IT
Preliminary
GS8320V18/32/36T-250/225/200/166/150/133
2M x 18, 1M x 32, 1M x 36
36Mb Sync Burst SRAMs
250 MHz–133 MHz
1.8 V VDD
1.8 V I/O
100-Pin TQFP
Commercial Temp
Industrial Temp
Rev: 1.02 10/2004
1/24
2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Features
FT pin for user-configurable flow through or pipeline
operation
Single Cycle Deselect (SCD) operation
1.8 V +10%/–10% core power supply
1.8 V I/O supply
LBO pin for Linear or Interleaved Burst mode
Internal input resistors on mode pins allow floating mode pins
Default to Interleaved Pipeline mode
Byte Write (BW) and/or Global Write (GW) operation
Internal self-timed write cycle
Automatic power-down for portable applications
JEDEC-standard 100-lead TQFP package
Pb-Free 100-lead TQFP package available
Functional Description
Applications
The GS8320V18/32/36T is a 37,748,736-bit high performance
synchronous SRAM with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device
now finds application in synchronous SRAM applications,
ranging from DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the rising-
edge-triggered Data Output Register.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS8320V18/32/36T operates on a 1.8 V power supply. All
input are 1.8 V compatible. Separate output power (VDDQ)
pins are used to decouple output noise from the internal circuits
and are 1.8 V compatible.
Parameter Synopsis
-250 -225 -200 -166 -150 -133 Unit
Pipeline
3-1-1-1
tKQ
tCycle
2.5
4.0
2.7
4.4
3.0
5.0
3.5
6.0
3.8
6.6
4.0
7.5
ns
Curr (x18)
Curr (x32/x36)
285
350
265
320
245
295
220
260
210
240
185
215
mA
Flow
Through
2-1-1-1
tKQ
tCycle
6.5
7.0
7.5
8.0
8.5
ns
Curr (x18)
Curr (x32/x36)
205
235
195
225
185
210
175
200
165
190
155
175
mA
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS8320V32GT-200 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 36MBIT 1MX32 7.5NS/3NS 100TQFP - Trays
GS8320V32GT-200I 制造商:GSI 制造商全稱(chēng):GSI Technology 功能描述:2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs
GS8320V32GT-225 制造商:GSI 制造商全稱(chēng):GSI Technology 功能描述:2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs
GS8320V32GT-225I 制造商:GSI 制造商全稱(chēng):GSI Technology 功能描述:2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs
GS8320V32GT-250 制造商:GSI 制造商全稱(chēng):GSI Technology 功能描述:2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs
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