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參數(shù)資料
| 型號： | GS8320V32GT-166IT |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | SRAM |
| 英文描述： | 1M X 32 CACHE SRAM, 8 ns, PQFP100 |
| 封裝： | LEAD FREE, TQFP-100 |
| 文件頁數(shù)： | 5/24頁 |
| 文件大?。?/td> | 655K |
| 代理商： | GS8320V32GT-166IT |
GS8320V18/32/36T-250/225/200/166/150/133
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 10/2004
13/24
2003, GSI Technology
Note:
These parameters are sample tested.
Logic Levels
Parameter
Symbol
Min.
Typ.
Max.
Unit
Notes
VDD Input High Voltage
VIH
0.6*VDD
—
VDD + 0.3
V1
VDD Input Low Voltage
VIL
–0.3
—
0.3*VDD
V1
VDDQ I/O Input High Voltage
VIHQ
0.6*VDD
—
VDDQ + 0.3
V1,3
VDDQ I/O Input Low Voltage
VILQ
–0.3
—
0.3*VDD
V1,3
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tKC.
3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V.
Capacitance
(TA = 25oC, f = 1 MHZ, VDD = 2.5 V)
Parameter
Symbol
Test conditions
Typ.
Max.
Unit
Input Capacitance
CIN
VIN = 0 V
45
pF
Input/Output Capacitance
CI/O
VOUT = 0 V
67
pF
20% tKC
VSS – 2.0 V
50%
VSS
VIH
Undershoot Measurement and Timing
Overshoot Measurement and Timing
20% tKC
VDD + 2.0 V
50%
VDD
VIL
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