- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄173638 > GS8321ZV36E-150T (GSI TECHNOLOGY) 1M X 36 ZBT SRAM, 8.5 ns, PBGA165 PDF資料下載
參數(shù)資料
| 型號： | GS8321ZV36E-150T |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | SRAM |
| 英文描述： | 1M X 36 ZBT SRAM, 8.5 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1 MM PITCH, FBGA-165 |
| 文件頁數(shù)： | 4/33頁 |
| 文件大?。?/td> | 1029K |
| 代理商： | GS8321ZV36E-150T |
第1頁第2頁第3頁當(dāng)前第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁
GS8321ZV18/32/36E-250/225/200/166/150/133
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04 4/2005
12/33
2003, GSI Technology
Burst Cycles
Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from
read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address
generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when
driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write
the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into
Load mode.
Burst Order
The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been
accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is low, a linear burst
sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables
below for details.
Mode Pin Functions
Mode Name
Pin
Name
State
Function
Burst Order Control
LBO
L
Linear Burst
H
Interleaved Burst
Power Down Control
ZZ
L or NC
Active
H
Standby, IDD = ISB
Note:
There are pull-up devices on the FT pin and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate
in the default states as specified in the above tables.
Note:
The burst counter wraps to initial state on the 5th clock.
Note:
The burst counter wraps to initial state on the 5th clock.
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00011011
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11000110
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00011011
2nd address
01
00
11
10
3rd address
10110001
4th address
11100100
Burst Counter Sequences
BPR 1999.05.18
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS832236AB-300T | 1M X 36 CACHE SRAM, PBGA119 |
| GS832472GC-150I | 512K X 72 CACHE SRAM, 10 ns, PBGA209 |
| GS832472GC-250T | 512K X 72 CACHE SRAM, 6 ns, PBGA209 |
| GS8342D08E-333T | 4M X 8 STANDARD SRAM, 0.45 ns, PBGA165 |
| GS8342Q08AE-278 | 4M X 8 DDR SRAM, 0.45 ns, PBGA165 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS8321ZV36E-166 | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 36MBIT 1MX36 8NS/3.5NS 165FBGA - Trays |
| GS8321ZV36E-166I | 制造商:GSI 制造商全稱:GSI Technology 功能描述:36Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8321ZV36E-200 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:36Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8321ZV36E-200I | 制造商:GSI 制造商全稱:GSI Technology 功能描述:36Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8321ZV36E-225 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:36Mb Pipelined and Flow Through Synchronous NBT SRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。