參數(shù)資料
型號(hào)： GS8342TT06BGD-500T
廠商： GSI TECHNOLOGY
元件分類(lèi)： SRAM
英文描述： 4M X 8 DDR SRAM, 0.45 ns, PBGA165
封裝： 13 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165
文件頁(yè)數(shù)： 1/30頁(yè)
文件大?。?/td> 267K
代理商： GS8342TT06BGD-500T
36Mb SigmaDDRTM-II+
Burst of 2 SRAM
550 MHz–350 MHz
1.8 V VDD
1.8 V or 1.5 V I/O
165-Bump BGA
Commercial Temp
Industrial Temp
Rev: 1.00 5/2011
1/30
2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8342TT06/11/20/38BD-550/500/450/400/350
Features
2.5 Clock Latency
Simultaneous Read and Write SigmaDDRTM Interface
JEDEC-standard pinout and package
Double Data Rate interface
Byte Write controls sampled at data-in time
Burst of 2 Read and Write
Dual-Range On-Die Termination (ODT) on Data (D), Byte
Write (BW), and Clock (K, K) inputs
1.8 V +100/–100 mV core power supply
1.5 V or 1.8 V HSTL Interface
Pipelined read operation
Fully coherent read and write pipelines
ZQ pin for programmable output drive strength
Data Valid Pin (QVLD) Support
IEEE 1149.1 JTAG-compliant Boundary Scan
165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
RoHS-compliant 165-bump BGA package available
SigmaDDR-II Family Overview
The GS8342TT06/11/20/38BD are built in compliance with
the SigmaDDR-II+ SRAM pinout standard for Common I/O
synchronous SRAMs. They are 37,748,736-bit (36Mb)
SRAMs. The GS8342TT06/11/20/38BD SigmaDDR-II+
SRAMs are just one element in a family of low power, low
voltage HSTL I/O SRAMs designed to operate at the speeds
needed to implement economical high performance
networking systems.
Clocking and Addressing Schemes
The GS8342TT06/11/20/38BD SigmaDDR-II+ SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer.
Because Common I/O SigmaDDR-II+
RAMs always transfer
data in two packets, A0 is internally set to 0 for the first read
or write transfer, and automatically incremented by 1 for the
next transfer. Because the LSB is tied off internally, the
address field of a SigmaDDR-II+ B2
RAM is always one
address pin less than the advertised index depth force return
(e.g., the 2M x 18 has a 1M addressable index).
Parameter Synopsis
-550
-500
-450
-400
-350
tKHKH
1.81 ns
2.0 ns
2.2 ns
2.5 ns
2.86 ns
tKHQV
0.45 ns
相關(guān)PDF資料
PDF描述
GS841Z36CGT-166IT 128K X 36 ZBT SRAM, 7 ns, PQFP100
GS842Z18CB-250T 256K X 18 ZBT SRAM, 5.5 ns, PBGA119
GS8641ZV18GE-200 4M X 18 ZBT SRAM, 7.5 ns, PBGA165
GS8644Z18GE-225T 4M X 18 ZBT SRAM, 6.5 ns, PBGA165
GS8662QT10BD-200I 8M X 9 QDR SRAM, 0.45 ns, PBGA165
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS8342TT11BD-500 制造商:GSI Technology 功能描述:165 FBGA - Bulk
GS8342TT11BD-500I 制造商:GSI Technology 功能描述:165 FBGA - Bulk
GS8342TT11BD-550 制造商:GSI Technology 功能描述:165 FBGA - Bulk
GS8342TT11BD-550I 制造商:GSI Technology 功能描述:165 FBGA - Bulk
GS8342TT20BD-500 制造商:GSI Technology 功能描述:165 FBGA - Bulk
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*