參數(shù)資料
型號: GS84118T-150
英文描述: x18 Synchronous SRAM
中文描述: x18同步SRAM
文件頁數(shù): 4/30頁
文件大?。?/td> 584K
代理商: GS84118T-150
Rev: 1.05 7/2001
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
4/30
1999, Giga Semiconductor, Inc.
GS84118T/B-166/150/130/100
TQFP Pin Description
Pin Location
Symbol
Description
37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 80, 48,
47, 46, 45, 44, 49, 50
A0–A17
Address Input Signals—Inputs are registered and must meet
setup and hold times, as specified on
page 11
.
89
CLK
Clock Input Signal
87
BWE
Byte Write Enable Signal—The byte write enable signal
needs to be combined with one of the four byte write signals
for a write operation to occur.
93
BW1
Byte Write signal for data outputs 1 thru 8
94
BW2
Byte Write signal for data outputs 9 thru 16
88
GW
Global Write Enable
92, 97, 98
CE1,CE2, CE3
Chip Enables
86
OE
Output Enable
83
ADV
Burst address advance
84, 85
ADSP, ADSC
Address status signals
58, 59, 62 ,63, 68, 69, 72, 73, 8, 9, 12, 13, 18,
19, 22, 23
DQ1–DQ16
Data Input and Output pins
74, 24
DQP1–DQP2
Parity Input and Output pins
53
MATCH
Match Output
51
MOE
Match Output Enable
52
DE
Data Enable—Data input registers are updated only when DE
is active.
64
ZZ
Power down control—Application of ZZ will result in a low
standby power consumption.
14
FT
Flow Through or Pipeline mode
31
LBO
Linear Order Burst mode
38
TMS
Test Mode Select
39
TDI
Test Data In
42
TDO
Test Data Out
43
TCK
Test Clock
15, 41, 65, 91
V
DD
3.3 V power supply
5,10,17, 21, 26, 40, 55, 60, 67, 71,
76, 90
V
SS
Ground
4, 11, 20, 27, 54, 61, 70, 77
V
DDQ
2.5 V/3.3 V output power supply
1, 2, 3, 6, 7, 16, 25, 28, 29, 30,56, 57, 66, 75,
78, 79, 95, 96
NC
No Connect
相關(guān)PDF資料
PDF描述
GS84118T-166 x18 Synchronous SRAM
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