參數(shù)資料
型號(hào)： GS8642V18E-250
廠商： GSI TECHNOLOGY
元件分類： SRAM
英文描述： 4M X 18 CACHE SRAM, 6.5 ns, PBGA165
封裝： 17 X 15 MM, 1 MM PITCH, FBGA-165
文件頁(yè)數(shù)： 19/39頁(yè)
文件大?。?/td> 1168K
代理商： GS8642V18E-250
Product Preview
GS8642V18(B/E)/GS8642V36(B/E)/GS8642V72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00 9/2004
26/39
2004, GSI Technology
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after ZZ recovery time.
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing
Application Tips
Single and Dual Cycle Deselect
SCD devices (like this one) force the use of “dummy read cycles” (read cycles that are launched normally, but that are ended with
the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance, but their use usually
assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste
bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at
bank address boundary crossings), but greater care must be exercised to avoid excessive bus contention.
JTAG Port Operation
Overview
The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output
drivers are powered by VDDQ.
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG
Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected.
tZZR
tZZH
tZZS
Hold
Setup
tKL
tKH
tKC
CK
ADSP
ADSC
ZZ
相關(guān)PDF資料
PDF描述
GS8642ZV36GB-167IT 2M X 36 ZBT SRAM, 8 ns, PBGA119
GS864418GE-225IV 4M X 18 CACHE SRAM, 6.5 ns, PBGA165
GS8644V18GE-150 4M X 18 CACHE SRAM, 7.5 ns, PBGA165
GS8662S36BD-300I 2M X 36 STANDARD SRAM, 0.45 ns, PBGA165
GS8662S36BGD-300 2M X 36 STANDARD SRAM, 0.45 ns, PBGA165
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS8642V36GB-300 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 72MBIT 2MX36 5.5NS/2.3NS 119FBGA - Trays
GS8642V72C-167 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 1.8V 72MBIT 1MX72 8NS/3.5NS 209FBGA - Trays
GS8642V72C-167I 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 1.8V 72MBIT 1MX72 8NS/3.5NS 209FBGA - Trays
GS8642V72GC-200 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 1.8V 72MBIT 1MX72 7.5NS/3NS 209FBGA - Trays
GS8642V72GC-300 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 1.8V 72MBIT 1MX72 5.5NS/3NS 209FBGA - Trays
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