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參數(shù)資料
| 型號： | GS8642ZV36GB-167IT |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | SRAM |
| 英文描述： | 2M X 36 ZBT SRAM, 8 ns, PBGA119 |
| 封裝： | 22 X 14 MM, 1.27 MM PITCH, LEAD FREE, BGA-119 |
| 文件頁數(shù)： | 11/32頁 |
| 文件大?。?/td> | 1452K |
| 代理商： | GS8642ZV36GB-167IT |
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AC Electrical Characteristics
Parameter
Symbol
-300
-250
-200
-167
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Pipeline
Clock Cycle Time
tKC
3.3
—
4.0
—
5.0
—
6.0
—
ns
Clock to Output Valid
(x18/x36)
tKQ
—
2.3
—
2.5
—
3.0
—
3.5
ns
Clock to Output Valid
(x72)
tKQ
—
3.0
—
3.0
—
3.0
—
3.5
ns
Clock to Output Invalid
tKQX
1.5
—
1.5
—
1.5
—
1.5
—
ns
Clock to Output in Low-Z
tLZ1
1.5
—
1.5
—
1.5
—
1.5
—
ns
Setup time
tS
1.1
—
1.2
—
1.4
—
1.5
—
ns
Hold time
tH
0.1
—
0.2
—
0.4
—
0.5
—
ns
Flow
Through
Clock Cycle Time
tKC
5.5
—
6.5
—
7.5
—
8.0
—
ns
Clock to Output Valid
tKQ
—
5.5
—
6.5
—
7.5
—
8.0
ns
Clock to Output Invalid
tKQX
3.0
—
3.0
—
3.0
—
3.0
—
ns
Clock to Output in Low-Z
tLZ1
3.0
—
3.0
—
3.0
—
3.0
—
ns
Setup time
tS
1.5
—
1.5
—
1.5
—
1.5
—
ns
Hold time
tH
0.5
—
0.5
—
0.5
—
0.5
—
ns
Clock HIGH Time
tKH
1.0
—
1.3
—
1.3
—
1.3
—
ns
Clock LOW Time
tKL
1.2
—
1.5
—
1.5
—
1.5
—
ns
Clock to Output in
High-Z (x18/x36)
tHZ1
1.5
2.3
1.5
2.5
1.5
3.0
1.5
3.0
ns
Clock to Output in
High-Z (x72)
tHZ1
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
ns
G to Output Valid
(x18/x36)
tOE
—
2.3
—
2.5
—
3.0
—
3.5
ns
G to Output Valid
(x72)
tOE
—
3.0
—
3.0
—
3.0
—
3.5
ns
G to output in Low-Z
tOLZ1
0
—
0
—
0
—
0
—
ns
G to output in High-Z
(x18/36)
tOHZ1
—
2.3
—
2.5
—
3.0
—
3.0
ns
G to output in High-Z
(x72)
tOHZ1
—
3.0
—
3.0
—
3.0
—
3.0
ns
ZZ setup time
tZZS2
5
—
5
—
5
—
5
—
ns
ZZ hold time
tZZH2
1
—
1
—
1
—
1
—
ns
ZZ recovery
tZZR
20
—
20
—
20
—
20
—
ns
Product Preview
GS8642ZV18(B)/GS8642ZV36(B)/GS8642ZV72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 5/2005
19/32
2004, GSI Technology
Notes:
1. These parameters are sampled and are not 100% tested.
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
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