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    參數(shù)資料
    型號: GS864418GE-225IV
    廠商: GSI TECHNOLOGY
    元件分類: SRAM
    英文描述: 4M X 18 CACHE SRAM, 6.5 ns, PBGA165
    封裝: 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165
    文件頁數(shù): 18/33頁
    文件大?。?/td> 528K
    代理商: GS864418GE-225IV
    JTAG TAP Instruction Set Summary
    Instruction
    Code
    Description
    Notes
    EXTEST
    000
    Places the Boundary Scan Register between TDI and TDO.
    1
    IDCODE
    001
    Preloads ID Register and places it between TDI and TDO.
    1, 2
    SAMPLE-Z
    010
    Captures I/O ring contents. Places the Boundary Scan Register between TDI and
    TDO.
    Forces all RAM output drivers to High-Z.
    1
    RFU
    011
    Do not use this instruction; Reserved for Future Use.
    Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
    1
    SAMPLE/
    PRELOAD
    100
    Captures I/O ring contents. Places the Boundary Scan Register between TDI and
    TDO.
    1
    GSI
    101
    GSI private instruction.
    1
    RFU
    110
    Do not use this instruction; Reserved for Future Use.
    Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
    1
    BYPASS
    111
    Places Bypass Register between TDI and TDO.
    1
    Notes:
    1. Instruction codes expressed in binary, MSB on left, LSB on right.
    2. Default instruction automatically loaded at power-up and in test-logic-reset state.
    GS864418/36E-xxxV
    Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
    Rev: 1.07a 10/2009
    25/33
    2003, GSI Technology
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