參數(shù)資料
型號(hào): GS881E36BGT-250T
廠商: GSI TECHNOLOGY
元件分類: SRAM
英文描述: 256K X 36 CACHE SRAM, 5.5 ns, PQFP100
封裝: ROHS COMPLIANT, TQFP-100
文件頁(yè)數(shù): 6/39頁(yè)
文件大?。?/td> 815K
代理商: GS881E36BGT-250T
GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)
Rev: 1.04a 3/2009
14/39
2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Simplified State Diagram
First Write
First Read
Burst Write
Burst Read
Deselect
R
W
CR
CW
X
WR
R
WR
X
Simple
Syn
chronous
Operation
Simple
Burst
Synchronous
Operation
CR
R
CW
CR
Notes:
1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.
2. The upper portion of the diagram assumes active use of only the Enable (E1) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and
that ADSP is tied high and ADSC is tied low.
3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and
assumes ADSP is tied high and ADV is tied low.
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