參數(shù)資料
型號(hào): EP6101
廠商: Altera Corporation
英文描述: Classic EPLD Family(典型EPLD系列器件)
中文描述: 經(jīng)典系列可編程邏輯器件(典型可編程邏輯器件系列器件)
文件頁(yè)數(shù): 6/15頁(yè)
文件大小: 227K
代理商: EP6101
974
Altera Corporation
AN 78: Understanding MAX 5000 & Classic Timing
Classic Devices
The architecture for the Classic device family, which includes the EP610,
EP610I, EP910, EP910I , and EP1810 devices, provides registered and
combinatorial capabilities. Registers can be clocked from a global clock or
through a product-term array clock, and can be asynchronously cleared.
When the global clock is used, the output enable signal can be controlled
by a product term.
Figure 3
shows the timing model for these Classic
devices.
Figure 3. Classic Device Timing Model
If the register is bypassed, the delay between the logic array and the output buffer is zero.
Calculating
Timing Delays
You can calculate pin-to-pin timing delays for any device with the
appropriate timing model and internal timing parameters. Each external
timing parameter is calculated from a combination of internal timing
parameters.
Figure 4
shows the external timing parameters for the
MAX 5000 and Classic device families. Classic devices include the EP610,
EP610I, EP910, EP910I , and EP1810 devices only. To calculate the delay
for a signal that follows a different path through the device, refer to the
timing models shown in
Figures 1
through
3
to determine which internal
timing parameters to add together.
Register
t
SU
t
H
I/O
Delay
t
IO
Feedback
Delay
t
FD
Input
Delay
t
IN
Logic Array
Delay
t
LAD
t
CLR
Array Clock
Delay
t
IC
Output
Delay
t
OD
t
XZ
t
ZX
Global Clock
Delay
t
ICS
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