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參數(shù)資料
| 型號： | GS882Z18B-100I |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8Mb Pipelined and Flow Through Synchronous NBT SRAMs |
| 中文描述： | 8MB的流水線和流量，通過同步唑靜態(tài)存儲器 |
| 文件頁數(shù)： | 13/34頁 |
| 文件大?。?/td> | 802K |
| 代理商： | GS882Z18B-100I |
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Rev: 1.15 6/2001
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
13/34
1998, Giga Semiconductor, Inc.
Preliminary
.
GS882Z18/36B-11/100/80/66
written memory locations may well produce parity errors. Initialization of the memory should be implemented to avoid this issue.
In x18/x36 mode this SRAM includes a write data parity check that checks the validity of data coming into the RAM on write
cycles. In Flow Through mode, write data errors are reported in the cycle following the data input cycle. In Pipeline mode, write
data errors are reported one clock cycle later. (See
Write Parity Error Output Timing Diagram
.) The Data Parity Mode (DP) pin
must be tied high to set the RAM to check for even parity or low to check for odd parity. Read data parity is not checked by the
RAM as data. Validity is best established at the data’s destination. The Parity Error Output is an open drain output and drives low
to indicate a parity error. Multiple Parity Error Output pins may share a common pull-up resistor.
x32 Mode (PE = 1) Read Parity Error Output Timing Diagram
CK
Address A
Address B
Address C
Address D
Address E
Address F
D Out A
D Out B
D Out C
D Out D
D Out E
tKQ
tLZ
DQ
QE
F
P
D Out A
D Out B
D Out C
D Out D
tKQ
tLZ
DQ
QE
Err A
Err A
Err C
Err C
tHZ
tKQX
tHZ
tKQX
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| GS882Z18BD150 | 制造商:G.S.I. 功能描述: |
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| GS882Z18CB-200I | 制造商:GSI Technology 功能描述:SRAM SYNC SGL 2.5V/3.3V 9MBIT 512KX18 6.5NS/3NS 119FPBGA - Trays |
| GS882Z18CB-200IV | 制造商:GSI Technology 功能描述:SRAM SYNC SGL 1.8V/2.5V 9MBIT 512KX18 6.5NS/3NS 119FPBGA - Trays |
| GS882Z18CB-200V | 制造商:GSI Technology 功能描述:SRAM SYNC SGL 1.8V/2.5V 9MBIT 512KX18 6.5NS/3NS 119FPBGA - Trays |
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