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參數(shù)資料
| 型號(hào)： | GS882Z18B-100I |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8Mb Pipelined and Flow Through Synchronous NBT SRAMs |
| 中文描述： | 8MB的流水線和流量，通過(guò)同步唑靜態(tài)存儲(chǔ)器 |
| 文件頁(yè)數(shù)： | 6/34頁(yè) |
| 文件大?。?/td> | 802K |
| 代理商： | GS882Z18B-100I |
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Rev: 1.15 6/2001
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
6/34
1998, Giga Semiconductor, Inc.
Preliminary
.
GS882Z18/36B-11/100/80/66
The Byte Write Enable inputs (B
A
, B
B
, B
C,
and B
D
) determine which bytes will be written. All or none may be activated. A Write
Cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality,
matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At
the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is
required at the third rising edge of clock.
Flow Through Mode Read and Write Operations
Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a Read Cycle and the
use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after
new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow
Through mode the read pipeline is one cycle shorter than in Pipeline mode.
Write operations are initiated in the same way as well, but differ in that the write pipeline is one cycle shorter, preserving the ability
to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late
write protocol, in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address
and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of
clock.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS882Z18B-11 | 8Mb Pipelined and Flow Through Synchronous NBT SRAMs |
| GS882Z18B-11I | 8Mb Pipelined and Flow Through Synchronous NBT SRAMs |
| GS882Z18B-66 | 8Mb Pipelined and Flow Through Synchronous NBT SRAMs |
| GS882Z18B-66I | 8Mb Pipelined and Flow Through Synchronous NBT SRAMs |
| GS882Z18B-80 | 8Mb Pipelined and Flow Through Synchronous NBT SRAMs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS882Z18BD150 | 制造商:G.S.I. 功能描述: |
| GS882Z18CB-200 | 制造商:GSI Technology 功能描述:SRAM SYNC SGL 2.5V/3.3V 9MBIT 512KX18 6.5NS/3NS 119FPBGA - Trays |
| GS882Z18CB-200I | 制造商:GSI Technology 功能描述:SRAM SYNC SGL 2.5V/3.3V 9MBIT 512KX18 6.5NS/3NS 119FPBGA - Trays |
| GS882Z18CB-200IV | 制造商:GSI Technology 功能描述:SRAM SYNC SGL 1.8V/2.5V 9MBIT 512KX18 6.5NS/3NS 119FPBGA - Trays |
| GS882Z18CB-200V | 制造商:GSI Technology 功能描述:SRAM SYNC SGL 1.8V/2.5V 9MBIT 512KX18 6.5NS/3NS 119FPBGA - Trays |
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